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System Verilog Jobs

11 open positions · Updated 1 week ago

Average salary (USD/year): 161.3k–225k/yr

11 roles Senior 6, Mid 3, Lead 1, Principal 1 1–8 yrs experience Austin, TX +6 more Full-time newest 1 week ago

Also hiring: Python Verilog ASIC SoC TCL Xilinx Vivado

11 System Verilog roles across 3 companies, most in Other

Who is hiring (3 companies)

SpaceX (9) Ambiq (1) Graphcore (1)

Role types

Other (10) Management (1)

Work arrangement: 1 on-site · 10 not stated

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 11 of 11 positions

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Senior Engineer, FPGA

Drive the development of FPGA images for pre-silicon prototyping at Ambiq, focusing on energy-efficient semiconductor solutions.

Ambiq Singapore Published 2 months ago

C++ Xilinx Vivado MSPI Verilog USB

Flexible on stack

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DFT Engineer

Join Graphcore as a DFT Engineer to work on next-generation AI designs for data centers, contributing to the future of AI compute.

Graphcore Bristol, UK; Cambridge, UK Published 7 months ago

IJTAG Core Test Test Compression Verilog Shell

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AMS Verification Engineer (RFIC Engineering) Visa

Join SpaceX as an AMS Verification Engineer to develop cutting-edge RFICs for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 2 weeks ago

AMS Verilog-A RFIC Python UVM

Flexible on stack

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AMS Verification Engineer (RFIC Engineering) Visa

Join SpaceX as an AMS Verification Engineer to develop cutting-edge RFICs for the Starlink network.

SpaceX Irvine, CA $125k–$160k/yr Published 2 weeks ago

AMS Verilog-A RFIC Python UVM

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $160k–$225k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $170k–$235k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Apply →

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Manager, ASIC Design Engineering (Starshield Silicon) Visa

SpaceX Hawthorne, CA $190k–$245k/yr Published 4 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. RTL Design Engineer (Silicon Engineering) Visa

SpaceX Austin, TX Published 6 months ago

Verilog AHB ASIC Python System Verilog

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Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 5 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 5 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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