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System Verilog Jobs

13 open positions · Updated 2 weeks ago

Average salary (USD/year): 160k–233.9k/yr

13 roles Senior 7, Mid 4, Lead 1, Principal 1 1–10 yrs experience Austin, TX +7 more Full-time newest 2 weeks ago

Also hiring: Python Verilog TCL Xilinx Vivado Altera Quartus II ASIC

13 System Verilog roles across 4 companies, most in Other

Who is hiring (4 companies)

SpaceX (10) Ambiq (1) Etched (1) Graphcore (1)

Role types

Other (12) Management (1)

Work arrangement: 2 on-site · 11 not stated

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 13 of 13 positions

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 3 weeks ago

Verilog ASIC Python System Verilog SoC

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ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC Design Engineer to develop cutting-edge FPGAs and ASICs for the Starlink broadband internet system.

SpaceX Palo Alto, CA $135k–$175k/yr Published 3 weeks ago

C++ Xilinx Vivado Verilog C DSP

Flexible on stack

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop next-generation ASICs for space and ground infrastructures.

SpaceX Austin, TX Published 1 month ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$270k/yr Published 1 month ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for space and ground infrastructures.

SpaceX Irvine, CA $165k–$265k/yr Published 1 month ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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DFT (Design For Test) Engineer

Join Etched as a DFT Engineer to enhance testability and product quality in cutting-edge integrated circuits.

Etched San Jose Published 8 months ago

Tessent Encounter Test Python DFT Compiler Perl

Flexible on stack

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Senior Engineer, FPGA

Drive the development of FPGA images for pre-silicon prototyping at Ambiq, focusing on energy-efficient semiconductor solutions.

Ambiq Singapore Published 4 months ago

Xilinx Vivado MSPI Verilog USB C

Flexible on stack

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Silicon DFT Engineer — Multiple Levels

Join Graphcore as a DFT Engineer to work on next-generation AI designs for data centers, contributing to the future of AI compute.

Graphcore Bristol, UK; Cambridge, UK Published 9 months ago

IJTAG Core Test Test Compression Verilog Shell

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AMS Verification Engineer (RFIC Engineering) Visa

Join SpaceX as an AMS Verification Engineer to develop cutting-edge RFICs for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 2 months ago

AMS Verilog-A RFIC Python UVM

Flexible on stack

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AMS Verification Engineer (RFIC Engineering) Visa

Join SpaceX as an AMS Verification Engineer to develop cutting-edge RFICs for the Starlink network.

SpaceX Irvine, CA $125k–$160k/yr Published 2 months ago

AMS Verilog-A RFIC Python UVM

Flexible on stack

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Manager, ASIC Design Engineering (Starshield Silicon) Visa

SpaceX Hawthorne, CA $190k–$245k/yr Published 6 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 7 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 7 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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