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Spyglass Jobs

9 open positions · Updated 1 month ago

Average salary: 171.1k–235.6k/yr

Showing 9 of 9 positions

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Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Sr. ASIC Design Engineer (Starshield)

SpaceX Irvine, CA $160k–$225k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Sr. ASIC Design Engineer (Starshield)

SpaceX Palo Alto, CA $170k–$235k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Manager, ASIC Design Engineering (Starshield Silicon) Visa

SpaceX Hawthorne, CA $190k–$245k/yr Published 1 month ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Principal ASIC Design Engineer (Starshield)

SpaceX Palo Alto, CA $210k–$295k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Principal ASIC Design Engineer (Starshield) Visa

SpaceX Irvine, CA $200k–$285k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

New Graduate Engineer, ASIC Design (Starshield) Visa

Join SpaceX as a New Graduate Engineer in ASIC Design, working on advanced technologies for national security and space applications.

SpaceX USA $125k–$150k/yr Published 1 day ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

Flexible on stack

FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 2 weeks ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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