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Rtl Jobs in Irvine

12 open positions · Updated 3 weeks ago

Average salary: 167.5k–233.8k/yr

Showing 12 of 12 positions

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 3 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 2 months ago

APB Verilog AHB DSP Python

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Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $200k–$285k/yr Published 3 weeks ago

C++ Verilog Siemens Tessent RTL DFT

Flexible on stack

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$175k/yr Published 3 weeks ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$230k/yr Published 3 weeks ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Irvine, CA $160k–$220k/yr Published 2 weeks ago

FinFET bash ASIC Python Perl

Flexible on stack

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Irvine, CA $145k–$175k/yr Published 1 month ago

FinFET RTL Makefile ASIC Python

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Sr. ASIC Design Engineer (Starshield)

SpaceX Irvine, CA $160k–$225k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Irvine, CA $200k–$285k/yr Published 2 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$300k/yr Published 3 weeks ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Irvine, CA $200k–$285k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

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Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Irvine, CA $160k–$225k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

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