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Sr. Digital Implementation Engineer

Join Alif Semiconductor as a Sr. Digital Implementation Engineer to create turn-key solutions for Cellular IoT devices.

Location
Irvine, CA
Compensation
Not disclosed
Level
senior
Type
full time

Posted by employer 3 years ago

First seen on Joblaze 1 week ago

Last verified on the company career page 1 day ago

Not disclosed in this posting: compensation, years of experience, work arrangement, visa sponsorship.

Joblaze summary

In this role, the Sr. Digital Implementation Engineer develops comprehensive solutions for advanced Cellular IoT devices, focusing on the delivery of netlists to Physical Design. Proficiency in ASIC synthesis flow, including static timing analysis and design for test, is essential for ensuring the quality of the RTL database. This position is ideal for experienced engineers with a strong background in digital design and implementation. Alif Semiconductor offers a dynamic environment where innovation drives the development of next-generation technology.

Joblaze insights

Quick facts

What's the tech stack?
Joblaze extracted these technologies from the posting: ASIC, DFT, IP integration, RTL, STA.
What seniority level is this role?
Alif Semiconductor targets senior candidates for this position.
Is this full-time or contract?
Full-time for this Sr. Digital Implementation Engineer role at Alif Semiconductor.

From the original posting

Alif Semiconductor is revolutionizing the way secure connected AI-enabled embedded solutions are created. We are looking for motivated individuals who want to be involved in a fast-paced environment with cutting-edge technology. You will be responsible for creating turn-key solutions to support cutting-edge Cellular IoT device. This is a unique opportunity to define a groundbreaking new system with few legacy constraints. As a Sr. Digital Implementation Engineer, you will own the netlist delivery (to Physical Design) of various blocks and chip top level by ensuring the integrity and quality of the RTL database and robust hand-off methodology. This position requires expert knowledge of ASIC synthesis flow (including STA/DFT and IP integration).

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