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Verilog Jobs in Redmond

3 open positions · Updated 1 week ago

Average salary: 136.7k–188.3k/yr
3 roles Junior 1, Mid 1, Senior 1 1–5 yrs experience Redmond, WA Full-time newest 1 week ago
Also hiring: Python ASIC DSP SystemVerilog VHDL ADS

Showing 3 of 3 positions

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SpaceX
New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Redmond, WA $125k–$165k/yr Published 1 week ago
ADS Verilog DSP HFSS RTL
Flexible on stack
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SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $160k–$225k/yr Published 3 months ago
Verilog ASIC Python System Verilog SoC
Flexible on stack
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SpaceX
FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 3 months ago
C++ Xilinx Vivado Verilog DSP HDL simulators
Flexible on stack
Apply →

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