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Verilog Jobs in Sunnyvale

2 open positions · Updated 2 months ago

Average salary: 190k–265k/yr

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Sunnyvale, CA $170k–$235k/yr Published 2 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Principal DFT Engineer (Silicon Engineering) Visa

SpaceX Sunnyvale, CA $210k–$295k/yr Published 5 months ago

C++ Verilog Siemens Tessent UPF RTL

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