Joblaze summary

The Senior ASIC Physical Design Engineer at K2 Space plays a crucial role in the development of advanced system-on-chip (SoC) designs for next-generation satellites, engaging in the entire physical design process from synthesis to GDSII. This position requires expertise in industry-standard tools and a solid understanding of timing analysis and power optimization, making it ideal for professionals with 5 to 10 years of experience in ASIC design. The role suits engineers who thrive in collaborative, fast-paced environments and are eager to contribute to cutting-edge space technology.

Joblaze insights

Listed about 2 months ago — first seen on Joblaze September 3, 2026. Last confirmed on K2 Space's careers page November 2, 2026.
This exact title is also open at 1 other location at K2 Space: United States - Remote.
Salary band is above the typical range for comparable tech roles (median ~$129,011).
Starts above 75% of 1477 comparable senior other roles we track (median $140,054 across 200 companies).
ASIC appears in 0.8% of 4200 comparable senior other roles; FinFET appears in 0.1% of 4200 comparable senior other roles.

Quick facts

What's the salary range?: K2 Space lists $170,000–$250,000 for this role.
How much experience is required?: 5–10 years of relevant experience for this Senior ASIC Physical Design Engineer role.
What's the tech stack?: Joblaze extracted these technologies from the posting: ASIC, CPF, Cadence Innovus, DFT, FinFET, GDSII.
Does K2 Space sponsor work visas for this role?: Yes — the posting indicates visa sponsorship is available for the right candidate.
What seniority level is this role?: K2 Space targets senior candidates for this position.
Is this full-time or contract?: Full-time for this Senior ASIC Physical Design Engineer role at K2 Space.

From the original posting

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The Role

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
Develop and maintain scripts and automation to improve flow efficiency and consistency.
Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
Assist in chip-level integration, ECOs, and tapeout preparation.
Contribute to methodology development, tool evaluation, and flow documentation.
Support your product through production and spaceflight.

Required Qualifications 

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
5–10 years of experience in ASIC physical design for complex SoCs.
Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
Strong understanding of timing analysis, power optimization, and physical verification flows.
Experience with hierarchical or flat SoC design methodologies.
Familiarity with FinFET technologies.
Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Preferred Qualifications 

Exposure to radiation-hardened or space-qualified ASICs.
Experience with chip-package co-design or advanced packaging (2.5D/3D).
Familiarity with physical design service vendor management or offshore collaboration.
Experience with sign-off through TSMC.
Experience with Gate-All-Around technologies.
Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

Base salary range for this role is $170,000 – $250,000 + equity in the company
Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

Standard company text repeated across K2 Space's postings is omitted here.

Senior ASIC Physical Design Engineer

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