Joblaze summary

The Senior ASIC Design Verification Engineer at K2 Space is responsible for verifying the functionality and performance of custom silicon designs, engaging deeply with various engineering teams to shape first-generation silicon. Key skills include expertise in SystemVerilog, UVM, and simulation tools, along with a solid understanding of digital logic and hardware verification flows. This role is ideal for experienced professionals with over five years in ASIC verification, particularly those familiar with cross-functional collaboration in high-tech environments. K2 Space's ambitious plans for satellite production highlight the innovative and fast-paced nature of the team.

Joblaze insights

Listed about a month ago — first seen on Joblaze September 3, 2026. Last confirmed on K2 Space's careers page October 27, 2026.
This exact title is also open at 1 other location at K2 Space: United States - Remote.
Salary band is above the typical range for comparable tech roles (median ~$129,111).
Starts above 73% of 344 comparable senior other roles that list Python we track (median $150,000 across 64 companies). See Python salary trends
Python appears in 14.8% of 4126 comparable senior other roles; UVM appears in 0.3% of 4126 comparable senior other roles.

Quick facts

What's the salary range?: K2 Space lists $170,000–$250,000 for this role.
How much experience is required?: At least 5 years of relevant experience for this Senior ASIC Design Verification Engineer role.
What's the tech stack?: Joblaze extracted these technologies from the posting: Perl, Python, SystemVerilog, TCL, UVM.
What seniority level is this role?: K2 Space targets senior candidates for this position.
Is this full-time or contract?: Full-time for this Senior ASIC Design Verification Engineer role at K2 Space.

From the original posting

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The Role

We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.

Responsibilities

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments. Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
Participate in ASIC team interviews.
Contribute to advancement of DV methodologies and improvements.
Engage external IP providers and verification partners when needed.

Qualifications

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in ASIC/SoC verification.
Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).

Nice to Have

Experience with developing and integrating reference models.
Understanding of low power verification.
Familiarity with gate-level simulation and analog behavioral models.
Involvement in post-silicon validation planning and execution.
Experience working in cross-functional, geographically distributed teams.
Experience in space, telecom, or RF/digital mixed systems is a plus.

Compensation and Benefits:

Base salary range for this role is $170,000 – $250,000 + equity in the company
Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

Standard company text repeated across K2 Space's postings is omitted here.

Senior ASIC Design Verification Engineer

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