Joblaze summary

The Sr. IC Package Design Engineer at SpaceX focuses on developing advanced packaging solutions for custom ASICs and RFICs that support the Starlink satellite system. This role requires expertise in IC package design, signal integrity, and the use of design tools like Cadence APD+/SIP, making it suitable for engineers with over five years of relevant experience. The position demands strong problem-solving skills and the ability to collaborate with cross-functional teams to optimize designs for performance and manufacturability.

Joblaze insights

Listed today — first seen on Joblaze October 25, 2026. Last confirmed on SpaceX's careers page October 25, 2026.
This exact title is also open at 1 other location at SpaceX: Irvine, CA, United States.
ASIC appears in 1.1% of 2602 comparable senior other roles in United States; BGA appears in 0.1% of 2602 comparable senior other roles in United States.

Quick facts

Is the Sr. IC Package Design Engineer (Silicon Engineering) role remote?: No — this is an on-site role in Austin, TX, United States.
How much experience is required?: At least 5 years of relevant experience for this Sr. IC Package Design Engineer (Silicon Engineering) role.
Where is the role based?: SpaceX is hiring for this position in Austin, TX, United States.
What's the tech stack?: Joblaze extracted these technologies from the posting: ADS, ASIC, BGA, Cadence APD+, HFSS, RFIC.
Does SpaceX sponsor work visas for this role?: Yes — the posting indicates visa sponsorship is available for the right candidate.
What seniority level is this role?: SpaceX targets senior candidates for this position.
Is this full-time or contract?: Full-time for this Sr. IC Package Design Engineer (Silicon Engineering) role at SpaceX.

From the original posting

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. IC PACKAGE DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom in-house ASICs and RFICs for digital beam formers and modems.

RESPONSIBILITIES:

Own and drive advanced package selection, new product BGA configuration and package structure
Responsible for package/SIP layout, optimization, design verification and tapeout
Interface and coordinate with cross-functional groups throughout SpaceX on new product package selection, feasibility analysis and design
Work cross-functionally, understand trade-offs, constraints, and optimizing silicon floor plan, bump and package pin out
Simulate and optimize signal/power integrity and RF performance of the package design
Drive methodology, innovations, and productivity improvements in package design

BASIC QUALIFICATIONS:

Bachelor's degree in electrical engineering, computer engineering, or physics
5+ years of experience with IC package design

PREFERRED SKILLS AND EXPERIENCE:

Experience with Co-packaged Optics (CPO)
Thorough understanding of signal and power integrity fundamentals
Substrate design experience for RF, digital, high-speed and mixed signal die
Experience with Cadence APD+/SIP or similar design tools
Experience in package design electrical review, SI/PI analysis
Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, ADS
Experience in package design for manufacturing reviews
Familiar with BGA package substrate technologies
Strong problem solving skills with strong engineering fundamentals

ADDITIONAL REQUIREMENTS:

Ability to work extended hours or weekends as needed to meet mission critical deadlines

ITAR REQUIREMENTS:

Standard company text repeated across SpaceX's postings is omitted here.

Sr. IC Package Design Engineer (Silicon Engineering)

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