Join SpaceX as a Sr. ASIC Design Engineer to develop next-generation ASICs for space and ground infrastructures.
Posted by employer 2 days ago
First seen on Joblaze 1 hour ago
Last verified on the company career page 1 hour ago
Skills & Technologies
What you'll build
- Evaluate architectural trade-offs
- Define micro-architecture
- Implement RTL in Verilog/System Verilog
- Work closely with verification team
- Participate in silicon bring-up and validation
Must have
- Bachelor’s degree in electrical engineering, computer engineering, or computer science
- 5+ years of experience in RTL implementation
Nice to have
- Ability to solve complex problems
- ASIC/SoC system integration experience
- Experience with embedded CPU subsystems
- Experience with standard bus protocols
- Experience with high speed and low power design techniques
- Scripting skills
Practical constraints
- Ability to work extended hours or weekends as needed for mission critical deadlines
- ITAR requirements for U.S. citizenship or residency
Requirements
- Experience
- 5+ years
- Education
- Bachelor's degree
- Visa
- Sponsorship available
Not disclosed in this posting: compensation, work arrangement.
Joblaze summary
The Sr. ASIC Design Engineer at SpaceX focuses on developing advanced ASICs for both space and ground infrastructures, contributing to the Starlink broadband network. Key skills include RTL implementation in Verilog/System Verilog, system integration, and experience with high-speed, low-power design techniques. This role is suited for engineers with over five years of experience in ASIC design and a strong problem-solving mindset. The position involves collaboration with cross-disciplinary teams to enhance connectivity solutions globally.
Joblaze insights
- Listed today — first seen on Joblaze October 3, 2026. Last confirmed on SpaceX's careers page October 3, 2026.
- This exact title is also open at 2 other locations at SpaceX: Irvine, CA, United States, Redmond, WA, United States.
- Python appears in 16.6% of 2438 comparable senior other roles in United States; System Verilog appears in 0.3% of 2438 comparable senior other roles in United States.
Quick facts
- How much experience is required?
- At least 5 years of relevant experience for this Sr. ASIC Design Engineer (Silicon Engineering) role.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: ASIC, Python, SoC, System Verilog, Verilog.
- Does SpaceX sponsor work visas for this role?
- Yes — the posting indicates visa sponsorship is available for the right candidate.
- What seniority level is this role?
- SpaceX targets senior candidates for this position.
- Is this full-time or contract?
- Full-time for this Sr. ASIC Design Engineer (Silicon Engineering) role at SpaceX.
From the original posting
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Evaluate architectural trade-offs based on features, performance requirements and system limitations
- Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
- Work closely with verification team to ensure all aspects of the design are covered and verified
- Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
- Participate in silicon bring-up and validation
BASIC QUALIFICATIONS:
- Bachelor’s degree in electrical engineering, computer engineering, or computer science
- 5+ years of experience in RTL implementation
PREFERRED SKILLS AND EXPERIENCE:
- Ability to solve complex problems including clock domain crossings and power optimization
- ASIC/SoC system integration experience
- Experience with embedded CPU subsystems
- Experience with standard bus protocols (e.g. AXI, AHB, etc.)
- Experience with high speed and low power design techniques
- Scripting skills (e.g. Python, etc.)
- Experience with EDA tools such as HDL simulators and HDL Lint tools
- Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
- Enjoys being challenged and learning new skills
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours or weekends as needed for mission critical deadlines
ITAR REQUIREMENTS:
Standard company text repeated across SpaceX's postings is omitted here.