"digital asic design" Jobs

100 open tech roles matching “digital asic design”, taken straight from company career pages — not reposted from other job boards. Every listing is re-checked daily and closed roles are removed.

No "digital asic design" jobs in Berlin right now — showing "digital asic design" jobs in all locations.

Showing 20 of 100 results

Director - Post-Silicon Validation (Functional)

Lead a team in validating cutting-edge AI chips and platforms at Graphcore's new AI Engineering Campus in Austin.

Graphcore Austin, Texas, United States Published 3 months ago

PCIe C++ ARM LPDDR FPGA

Flexible on stack

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Manager, ASIC Design Engineering (Starshield Silicon) Visa

SpaceX Hawthorne, CA $190k–$245k/yr Published 5 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Redmond, WA $165k–$270k/yr Published 2 months ago

DSP Ka-band microwave SiGe RFIC

Flexible on stack

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Principal Embedded SW/FW Engineer (Bringup) - Bengaluru, multiple vacancies

Join Graphcore as a Principal Embedded SW/FW Engineer in Bengaluru, focusing on post-silicon validation of AI chips.

Graphcore Bengaluru, India Published 11 months ago

PCIe C++ ARM LPDDR FPGA

Flexible on stack

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RFIC Engineer (Starshield Silicon) Visa

Join SpaceX as an RFIC Engineer to develop next-generation RFICs for national security applications in a fast-paced environment.

SpaceX Hawthorne, CA $125k–$175k/yr Published 5 months ago

GaAs GaN Network Analyzers Vector Signal Analyzers spectrum analyzers

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Sr. Technical Project Lead (Silicon Engineering) Visa

Lead complex silicon projects at SpaceX, developing cutting-edge ASICs for Starlink's global connectivity solutions.

SpaceX Redmond, WA $165k–$260k/yr Published 3 months ago

RF Design Project Management Silicon Engineering PCB FPGA

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Principal Debug Validation Engineer

Join a collaborative team to validate high-performance AI chips and support new product introductions in Austin.

Graphcore Austin, Texas, United States Published 3 months ago

PCIe C++ ARM LPDDR FPGA

Flexible on stack

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Post Silicon Validation Engineer

Join Graphcore as a Post Silicon Validation Engineer to validate cutting-edge AI chips and mentor a collaborative engineering team.

Graphcore Bristol, UK Published 11 months ago

PCIe C++ ARM LPDDR FPGA

Flexible on stack

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Sr. Technical Project Lead (Silicon Engineering) Visa

Lead complex silicon projects at SpaceX, developing next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$260k/yr Published 3 months ago

RF Design Project Management Silicon Engineering PCB FPGA

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Sr. Technical Project Lead (Silicon Engineering) Visa

Lead complex silicon projects at SpaceX, developing next-generation ASICs for Starlink's global connectivity solutions.

SpaceX Palo Alto, CA $175k–$280k/yr Published 3 months ago

Project Management Digital ASIC Design Silicon Engineering PCB FPGA

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Sr. Technical Project Lead (Silicon Engineering) Visa

Lead complex silicon projects at SpaceX, driving the development of next-generation ASICs for Starlink's global connectivity.

SpaceX Austin, TX Published 3 months ago

Project Management Digital ASIC Design Silicon Engineering PCB FPGA

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Principal Debug Validation Engineer

Lead post-silicon debug and validation activities for next-generation AI compute silicon and systems at Graphcore.

Graphcore Bengaluru, India Published 3 months ago

PCIe C++ Lauterbach JTAG JLink

Flexible on stack

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Senior Debug Validation Engineer

Lead post-silicon debug and validation activities for next-generation AI compute silicon and systems at Graphcore.

Graphcore Bengaluru, India Published 3 months ago

PCIe C++ Lauterbach JTAG JLink

Flexible on stack

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Staff Embedded SW/FW Engineer (Bringup) - Bengaluru

Join Graphcore as a Staff Embedded SW/FW Engineer to develop C code for validating high-performance AI chips in Bengaluru.

Graphcore Bengaluru, India Published 11 months ago

PCIe C++ ARM LPDDR FPGA

Flexible on stack

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Staff Analog Mixed-Signal Design and Modelling Engineer Hybrid

Join IonQ as a Senior Staff Analog Mixed-Signal Design and Modelling Engineer to shape the future of quantum computing.

IonQ Oxford, England, United Kingdom Published 2 months ago

Verilog-A Verilog-AMS Python Cadence AMS Designer SystemVerilog

Flexible on stack

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Principal Engineer, AI Satellites (Starmind) Visa

Join SpaceX as a Principal Engineer to develop cutting-edge RFICs for the Starmind satellite constellation.

SpaceX Bastrop, TX Published 2 months ago

RF Analog Mixed-Signal DSP microwave

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Principal RFIC Engineer (Starshield Silicon)

Join SpaceX as a Principal RFIC Engineer to develop next-generation RFICs for national security applications.

SpaceX Irvine, CA $210k–$340k/yr Published 3 weeks ago

RF GaAs IC design Analog GaN

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RFIC Engineer, AI Satellites (Starmind) Visa

Join SpaceX as an RFIC Engineer to develop next-generation RFICs for AI satellites, enhancing connectivity and performance in space.

SpaceX Bastrop, TX Published 2 months ago

C++ High-Speed Digital Systems ADS custom compute electronics Networking

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Principal RFIC Engineer (Starshield Silicon) Visa

Join SpaceX as a Principal RFIC Engineer to develop cutting-edge RFICs for national security applications in a fast-paced environment.

SpaceX Hawthorne, CA $210k–$340k/yr Published 1 month ago

GaAs GaN Network Analyzers Vector Signal Analyzers spectrum analyzers

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Sr. MMIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. MMIC Design Engineer to develop cutting-edge MMICs for the Starlink network, enabling global connectivity.

SpaceX Redmond, WA $165k–$270k/yr Published 2 months ago

C++ RF GaAs ADS GaN

Flexible on stack

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