joblaze

Showing 3 of 3 results

SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $125k–$175k/yr Published 1 month ago
Python UVM SystemVerilog MATLAB
Flexible on stack
Apply →
SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$230k/yr Published 1 month ago
VMM Python UVM OVM
Flexible on stack
Apply →
SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $210k–$300k/yr Published 1 month ago
FPGA ASIC VMM Python UVM
Flexible on stack
Apply →

Related searches

Uvm Uvm Remote Senior Uvm Junior Uvm Uvm in London Uvm in New York Uvm in Redmond Python in Redmond Vmm in Redmond