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Senior Uvm Jobs

6 open positions · Updated 3 days ago

Average salary: 167.5k–231.7k/yr

Showing 6 of 6 positions

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Sr. Design Verification Engineer (Silicon Engineering) Visa

VMM Python UVM OVM

Redmond, WA

$165k–$230k/yr

Published 3 months ago Apply →

Sr. Design Verification Engineer (Silicon Engineering) Visa

VMM Python UVM OVM

Sunnyvale, CA

$170k–$230k/yr

Published 3 months ago Apply →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

VMM Python UVM OVM

Irvine, CA

$165k–$230k/yr

Published 3 months ago Apply →

Sr. ASIC/SOC Verification Engineer (Silicon Engineering) Visa

VMM Python UVM OVM

Sunnyvale, CA

$175k–$240k/yr

Published 3 months ago Apply →

Sr. ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

Palo Alto, CA

$170k–$235k/yr

Published 1 week ago Apply →

Sr. ASIC Design Verification Engineer (Starshield) Visa

Python UVM SystemVerilog MATLAB

Hawthorne, CA

$160k–$225k/yr

Published 2 weeks ago Apply →

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