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Uvm Jobs

13 open positions · Updated 1 week ago

Average salary: 202k–316k/yr

Showing 13 of 13 positions

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SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 2 weeks ago
Python UVM SystemVerilog MATLAB
Flexible on stack
Apply →
SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 2 weeks ago
Python UVM SystemVerilog MATLAB
Flexible on stack
Apply →
SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 2 weeks ago
Python UVM SystemVerilog MATLAB
Flexible on stack
Apply →
SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 2 weeks ago
Python UVM SystemVerilog MATLAB
Flexible on stack
Apply →
SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$260k/yr Published 2 weeks ago
ASIC VMM Python UVM OVM
Flexible on stack
Apply →
SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$260k/yr Published 2 weeks ago
ASIC VMM Python UVM OVM
Flexible on stack
Apply →
SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 weeks ago
ASIC VMM Python UVM OVM
Flexible on stack
Apply →
SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 2 weeks ago
ASIC VMM Python UVM OVM
Flexible on stack
Apply →
SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 2 months ago
FPGA ASIC VMM Python UVM
Flexible on stack
Apply →
SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$300k/yr Published 2 months ago
FPGA ASIC VMM Python UVM
Flexible on stack
Apply →
SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 2 months ago
FPGA ASIC VMM Python UVM
Flexible on stack
Apply →
SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $210k–$300k/yr Published 2 months ago
FPGA ASIC VMM Python UVM
Flexible on stack
Apply →
Anthropic
Research Engineer, Chip Design RL (Reinforcement Learning) Remote Visa

Join Anthropic as a Research Engineer to advance AI models' silicon design capabilities within a hybrid work environment.

Anthropic San Francisco, CA | New York City, NY $500k–$850k/yr Published 2 weeks ago
EDA RTL FPGA reinforcement learning ASIC
Flexible on stack
Apply →

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