"memory subsystems" Jobs
54 open tech roles matching “memory subsystems”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: Python, C++, Linux. Every listing is re-checked daily and closed roles are removed.
Showing 20 of 54 results
Join Applied Intuition to develop core OS components for future vehicles as a Senior Software Engineer.
Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.
Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.
Join SpaceX as a Sr. ASIC DFT Engineer to develop next-generation ASICs for the Starlink network, enabling global connectivity.
Join Neko Health as a Senior Electronics Design Engineer to design and own electronics for sensor-dense medical systems.
Lead post-silicon debug and validation activities for next-generation AI compute silicon and systems at Graphcore.
Own DRTM integration and platform security for AI infrastructure at Anthropic, collaborating with firmware and hardware teams.
Lead the architecture definition for next-generation ultra-low-power AI SoCs at Ambiq.
Join Neo Security as a Senior Low Level Engineer to lead development projects in AI-assisted security solutions across multiple OS platforms.
Lead post-silicon debug and validation activities for next-generation AI compute silicon and systems at Graphcore.
Lead validation strategy and execution for advanced AI compute silicon and systems at Graphcore.
Lead validation strategy and execution for advanced AI compute silicon and systems at Graphcore.
Lead the RAS validation strategy for GPU server platforms in a pioneering space-based solar energy company.
Lead validation strategy and execution for power and performance of advanced AI compute silicon and systems.
Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.
Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.
Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.