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RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 2 months ago

APB Verilog AHB DSP Python

FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 1 week ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

FPGA Engineer (Starshield) Visa

SpaceX Hawthorne, CA $120k–$170k/yr Published 3 months ago

TCP C++ Ethernet 802.3 Verilog Xilinx SoC FPGA

Sr. FPGA Engineer (Starshield) Visa

SpaceX Hawthorne, CA $160k–$225k/yr Published 3 months ago

C++ Verilog DSP FPGA SystemVerilog

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