Vhdl Jobs

8 open positions · Updated 1 week ago

Average salary: 90.7k–121.4k/yr

8 roles Intern 3, Junior 3, Mid 2 0–2 yrs experience Flexible - Any SpaceX Site +4 more Full-time, Internship newest 1 week ago

Also hiring: Python Verilog SystemVerilog C++ ADS ASIC

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Irvine, CA $125k–$160k/yr Published 1 week ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 week ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Redmond, WA $125k–$165k/yr Published 1 week ago

ADS Verilog DSP HFSS RTL

Flexible on stack

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Spring 2027 Silicon Engineering Internship/Co-op Visa

Join SpaceX as a silicon engineering intern to work on cutting-edge chip design and development for space applications.

SpaceX Flexible - Any SpaceX Site $30–$40/yr Published 2 weeks ago

C++ Verilog ANSYS COMSOL SPICE

Flexible on stack

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Summer 2027 Silicon Engineering Internship/Co-op Visa

Join SpaceX as a silicon engineering intern to work on custom silicon and hardware for space applications.

SpaceX Flexible - Any SpaceX Site $30–$40/yr Published 2 weeks ago

C++ Verilog ANSYS COMSOL SPICE

Flexible on stack

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American Tech Fellowship Remote

Join the American Tech Fellowship to gain skills in deploying AI software and explore opportunities for full-time roles at Palantir.

Palantir North America Published 1 year ago

TypeScript C++ Labview JavaScript Verilog

Flexible on stack

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 3 months ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 5 months ago

APB Verilog AHB DSP Python

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