Ovm Jobs

8 open positions · Updated 1 month ago

Average salary: 189.2k–285k/yr

8 roles Principal 4, Senior 4 5–10 yrs experience Austin, TX +3 more Full-time newest 1 month ago

Also hiring: ASIC Python UVM VMM FPGA

Showing 8 of 8 positions

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$260k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$260k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$300k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $210k–$300k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →