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Rtl Jobs in Palo Alto

2 open positions · Updated 1 week ago

2 roles Junior 1, Mid 1 1 yrs experience Palo Alto, CA Full-time newest 1 week ago
Also hiring: ASIC SystemVerilog Verilog ADS ATPG C/C++

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SpaceX
New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 week ago
ADS Verilog HFSS RTL Momentum
Flexible on stack
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SpaceX
ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 2 weeks ago
Verilog UPF RTL DFT ASIC
Flexible on stack
Apply →

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