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Verilog Jobs

49 open positions · Updated 3 days ago

Average salary (USD/year): 152.0k–235.6k/yr

49 roles Mid 14, Senior 13, Intern 10, Principal 5, Staff 4, Lead 2, Director 1 0–20 yrs experience Austin, TX +21 more Full-time, Internship newest 3 days ago

Also hiring: Python SystemVerilog C++ TCL FPGA C

49 Verilog roles across 14 companies, most in Other; 2% fully remote; typical advertised salary $145k

Who is hiring (14 companies)

SpaceX (18) Ambiq (7) Astranis (6) Etched (4) Graphcore (2)

Role types

Other (42) AI/ML (4) Design (2) Management (1)

Work arrangement: 1 fully remote · 1 hybrid · 9 on-site · 38 not stated

Advertised salaries: p25 $125k · median $145k · p75 $175k (from 22 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 20 of 49 positions

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Director, Logical Design

Lead the design and development of complex SoCs for next-generation AI acceleration platforms at Graphcore.

Graphcore Bengaluru, India Published 4 days ago

Verilog Digital Design ASIC SystemVerilog Microarchitecture

Flexible on stack

Sr. FPGA Design Engineer

Join Reliable Robotics as a Sr. FPGA Design Engineer to enhance aviation safety through innovative technology.

Reliable Robotics Corporation Mountain View, CA Published 1 week ago

Verilog SystemVerilog VHDL

FPGA Engineer (Starshield)

Design and develop FPGAs for SpaceX's satellite constellation, focusing on safety-critical logic and communications systems.

SpaceX Hawthorne, CA $125k–$195k/yr Published 2 weeks ago

C++ Verilog C Xilinx SoC FPGA Python

Flexible on stack

DFT Engineer

Join Ricursive Intelligence as a DFT Engineer to shape the future of chip design with AI-driven methodologies.

Ricursive Intelligence Palo Alto Published 2 weeks ago

IJTAG Verilog DFT Python TCL

Flexible on stack

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 weeks ago

Verilog ASIC Python System Verilog SoC

ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC Design Engineer to develop cutting-edge FPGAs and ASICs for the Starlink broadband internet system.

SpaceX Palo Alto, CA $135k–$175k/yr Published 2 weeks ago

C++ Xilinx Vivado Verilog C DSP

Flexible on stack

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$270k/yr Published 4 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for space and ground infrastructures.

SpaceX Irvine, CA $165k–$265k/yr Published 4 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

Sr. ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Engineer to develop next-generation ASICs for space and ground infrastructures.

SpaceX Austin, TX Published 4 weeks ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

DFT Intern

Join Ambiq as a DFT Intern to gain hands-on experience in low power DFT implementation and verification for ultra-low power chips.

Ambiq Singapore Published 4 weeks ago

Verilog Shell Python TCL SystemVerilog

FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 1 month ago

C++ Xilinx Vivado Verilog C DSP

Flexible on stack

FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 1 month ago

C++ Xilinx Vivado Verilog C DSP

Flexible on stack

FPGA Intern (Winter 2027)

Join Astranis as an FPGA Intern to work on hardware development for advanced satellite technology.

Astranis San Francisco $29–$29/hr Published 1 month ago

Verilog Xilinx Vivado FPGA UVM

Flexible on stack

FPGA Associate (Winter 2027)

Join Astranis as an FPGA Associate to work on hardware development for advanced satellite technology.

Astranis San Francisco $1.9k–$1.9k/wk Published 1 month ago

Verilog Vivado IDE Xilinx FPGA TCL

Flexible on stack

FPGA Intern (Summer 2027) Visa

Join Astranis as an FPGA Intern to work on hardware development for advanced satellite technology.

Astranis San Francisco $29–$29/hr Published 1 month ago

Verilog Vivado IDE Xilinx FPGA UVM

Flexible on stack

FPGA Associate (Summer 2027)

Join Astranis as an FPGA Associate to work on hardware development for advanced satellite systems.

Astranis San Francisco $1.9k–$1.9k/wk Published 1 month ago

Verilog Xilinx Vivado FPGA UVM

Flexible on stack

Intern, Software Engineering, 2027 Visa

Join Cowboy Space Corporation as a Software Engineering Intern to tackle complex technical challenges in space-based solar energy.

Cowboy Space Corporation San Carlos, California $1.8k–$1.8k/wk Published 1 month ago

C++ Verilog C F Prime cFS

Flexible on stack

Silicon Validation Engineer, Software

Join Etched as a Silicon Validation Engineer to develop firmware for AI/ML accelerator ASICs in a hands-on, onsite role.

Etched San Jose Published 1 month ago

C++ Verilog C CI/CD JTAG

Flexible on stack

ASIC Architect

Join Etched as an ASIC Architect to design next-generation AI accelerators with a focus on performance and efficiency.

Etched San Jose Published 1 year ago

C++ Verilog C gem5 AI/ML

Flexible on stack Heavy meetings

DFT Intern

Join Etched as a DFT Intern to refine DFT flow automation and contribute to chip-level regression in a fast-paced environment.

Etched San Jose Published 6 months ago

Verilog Python TCL SystemVerilog

Flexible on stack

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