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System Verilog Jobs at SpaceX

7 open positions · Updated 3 months ago

Average salary: 173.3k–240k/yr
7 of 2313 open roles Senior 5, Lead 1, Principal 1 5–8 yrs experience Austin, TX +4 more Full-time newest 3 months ago
Also hiring: Python Verilog ASIC SoC Altera Quartus II IES

Showing 7 of 7 positions

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SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 3 months ago
Verilog ASIC Python System Verilog SoC
Flexible on stack
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SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $170k–$235k/yr Published 3 months ago
Verilog ASIC Python System Verilog SoC
Flexible on stack
Apply →
SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $160k–$225k/yr Published 3 months ago
Verilog ASIC Python System Verilog SoC
Flexible on stack
Apply →
SpaceX
Manager, ASIC Design Engineering (Starshield Silicon) Visa
SpaceX Hawthorne, CA $190k–$245k/yr Published 3 months ago
Xilinx Vivado Verilog IES Altera Quartus II Spyglass
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SpaceX
Principal ASIC Design Engineer (Starshield) Visa
SpaceX Hawthorne, CA $200k–$285k/yr Published 4 months ago
Xilinx Vivado Verilog IES Altera Quartus II Spyglass
Apply →
SpaceX
Sr. ASIC Design Engineer (Starshield)
SpaceX Hawthorne, CA $160k–$225k/yr Published 4 months ago
Xilinx Vivado Verilog IES Altera Quartus II Spyglass
Apply →
SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa
SpaceX Austin, TX Published 5 months ago
Verilog AHB ASIC Python System Verilog
Apply →

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