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Asic Jobs at SpaceX

48 open positions · Updated 1 week ago

Average salary: 162.9k–240.6k/yr

48 of 2313 open roles Senior 24, Mid 9, Principal 8, Lead 4, Junior 3 1–10 yrs experience Austin, TX +5 more Full-time newest 1 week ago

Also hiring: Python CMOS FPGA Perl Verilog RFIC

Showing 20 of 48 positions

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Irvine, CA $125k–$160k/yr Published 1 week ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 week ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Redmond, WA $125k–$165k/yr Published 1 week ago

ADS Verilog DSP HFSS RTL

Flexible on stack

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Sr. DSP Systems Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. DSP Systems Engineer to develop cutting-edge ASICs for satellite broadband systems.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 week ago

C++ RF MIMO FPGA ASIC

Flexible on stack

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Sr. DSP Systems Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. DSP Systems Engineer to develop cutting-edge ASICs for satellite broadband systems.

SpaceX Irvine, CA $165k–$265k/yr Published 1 week ago

RF/wireless system design AI/ML FPGA C/C++ ASIC

Flexible on stack AI-first team

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ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 2 weeks ago

Verilog UPF RTL DFT ASIC

Flexible on stack

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Principal Engineer, AI Satellites (Starmind) Visa

Join SpaceX as a Principal Engineer to develop cutting-edge RFICs for the Starmind satellite constellation.

SpaceX Bastrop, TX Published 2 weeks ago

RF Analog Mixed-Signal DSP microwave

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ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 2 weeks ago

Verilog RTL DFT bash ASIC

Flexible on stack

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Electrical Design Engineer, Satellites Payload (Starlink) Visa

Join SpaceX as an Electrical Design Engineer to develop high-reliability electronics for the Starlink satellite communication network.

SpaceX Palo Alto, CA $115k–$185k/yr Published 2 weeks ago

C++ RF PAM4 PCB Physics

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Palo Alto, CA $220k–$355k/yr Published 3 weeks ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 3 weeks ago

C++ Verilog Siemens Tessent UPF DFT

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$340k/yr Published 3 weeks ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

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RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as an RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 1 month ago

Filters vector modulators low noise amplifiers Mixed-Signal Spread Spectrum

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Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $165k–$265k/yr Published 1 month ago

DSP QAM Ka-band QPSK APSK

Flexible on stack

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RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as an RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $125k–$195k/yr Published 1 month ago

Filters vector modulators low noise amplifiers power amplifiers DSP

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Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

Filters vector modulators low noise amplifiers Mixed-Signal Spread Spectrum

Flexible on stack

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Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Redmond, WA $165k–$270k/yr Published 1 month ago

DSP Ka-band microwave SiGe RFIC

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$260k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

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