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Verilog Jobs at SpaceX

19 open positions · Updated 1 week ago

Average salary: 140.0k–197.5k/yr

19 of 2313 open roles Senior 5, Mid 4, Principal 4, Junior 3, Intern 2, Lead 1 0–10 yrs experience Austin, TX +5 more Full-time, Internship newest 1 week ago

Also hiring: Python ASIC SystemVerilog System Verilog VHDL C++

Showing 19 of 19 positions

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Irvine, CA $125k–$160k/yr Published 1 week ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 week ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Redmond, WA $125k–$165k/yr Published 1 week ago

ADS Verilog DSP HFSS RTL

Flexible on stack

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ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 2 weeks ago

Verilog UPF RTL DFT ASIC

Flexible on stack

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ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 2 weeks ago

Verilog RTL DFT bash ASIC

Flexible on stack

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Spring 2027 Silicon Engineering Internship/Co-op Visa

Join SpaceX as a silicon engineering intern to work on cutting-edge chip design and development for space applications.

SpaceX Flexible - Any SpaceX Site $30–$40/yr Published 2 weeks ago

C++ Verilog ANSYS COMSOL SPICE

Flexible on stack

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Summer 2027 Silicon Engineering Internship/Co-op Visa

Join SpaceX as a silicon engineering intern to work on custom silicon and hardware for space applications.

SpaceX Flexible - Any SpaceX Site $30–$40/yr Published 2 weeks ago

C++ Verilog ANSYS COMSOL SPICE

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$340k/yr Published 3 weeks ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 3 weeks ago

C++ Verilog Siemens Tessent UPF DFT

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Palo Alto, CA $220k–$355k/yr Published 3 weeks ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $160k–$225k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $170k–$235k/yr Published 3 months ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$175k/yr Published 3 months ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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Manager, ASIC Design Engineering (Starshield Silicon) Visa

SpaceX Hawthorne, CA $190k–$245k/yr Published 3 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. RTL Design Engineer (Silicon Engineering) Visa

SpaceX Austin, TX Published 5 months ago

Verilog AHB ASIC Python System Verilog

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Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 4 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 4 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 5 months ago

APB Verilog AHB DSP Python

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