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Uvm Jobs at SpaceX

12 open positions · Updated 1 month ago

Average salary: 168.9k–256.7k/yr
12 of 2313 open roles Mid 4, Principal 4, Senior 4 1–10 yrs experience Austin, TX +3 more Full-time newest 1 month ago
Also hiring: Python ASIC OVM VMM FPGA MATLAB

Showing 12 of 12 positions

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SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago
Python UVM SystemVerilog MATLAB
Flexible on stack
Apply →
SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 1 month ago
Python UVM SystemVerilog MATLAB
Flexible on stack
Apply →
SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$260k/yr Published 1 month ago
ASIC VMM Python UVM OVM
Flexible on stack
Apply →
SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago
ASIC VMM Python UVM OVM
Flexible on stack
Apply →
SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 1 month ago
Python UVM SystemVerilog MATLAB
Flexible on stack
Apply →
SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago
ASIC VMM Python UVM OVM
Flexible on stack
Apply →
SpaceX
Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$260k/yr Published 1 month ago
ASIC VMM Python UVM OVM
Flexible on stack
Apply →
SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 1 month ago
Python UVM SystemVerilog MATLAB
Flexible on stack
Apply →
SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 months ago
FPGA ASIC VMM Python UVM
Flexible on stack
Apply →
SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 3 months ago
FPGA ASIC VMM Python UVM
Flexible on stack
Apply →
SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $210k–$300k/yr Published 3 months ago
FPGA ASIC VMM Python UVM
Flexible on stack
Apply →
SpaceX
Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$300k/yr Published 3 months ago
FPGA ASIC VMM Python UVM
Flexible on stack
Apply →

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