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Xilinx Vivado Jobs

7 open positions · Updated 2 weeks ago

Average salary (USD/year): 155.8k–220.8k/yr
7 roles Mid 3, Senior 2, Lead 1, Principal 1 1–8 yrs experience Hawthorne, CA +4 more Full-time newest 2 weeks ago
Also hiring: Python Verilog Altera Quartus II System Verilog C bash

Showing 7 of 7 positions

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SpaceX
ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC Design Engineer to develop cutting-edge FPGAs and ASICs for the Starlink broadband internet system.

SpaceX Palo Alto, CA $135k–$175k/yr Published 2 weeks ago
C++ Xilinx Vivado Verilog C DSP
Flexible on stack
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SpaceX
FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 4 weeks ago
C++ Xilinx Vivado Verilog C DSP
Flexible on stack
Apply →
SpaceX
FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 4 weeks ago
C++ Xilinx Vivado Verilog C DSP
Flexible on stack
Apply →
Ambiq
Senior Engineer, FPGA

Drive the development of FPGA images for pre-silicon prototyping at Ambiq, focusing on energy-efficient semiconductor solutions.

Ambiq Singapore Published 4 months ago
Xilinx Vivado MSPI Verilog USB C
Flexible on stack
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SpaceX
Manager, ASIC Design Engineering (Starshield Silicon) Visa
SpaceX Hawthorne, CA $190k–$245k/yr Published 6 months ago
Xilinx Vivado Verilog IES Altera Quartus II Spyglass
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SpaceX
Sr. ASIC Design Engineer (Starshield)
SpaceX Hawthorne, CA $160k–$225k/yr Published 6 months ago
Xilinx Vivado Verilog IES Altera Quartus II Spyglass
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SpaceX
Principal ASIC Design Engineer (Starshield) Visa
SpaceX Hawthorne, CA $200k–$285k/yr Published 6 months ago
Xilinx Vivado Verilog IES Altera Quartus II Spyglass
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