Drive the development of FPGA images for pre-silicon prototyping at Ambiq, focusing on energy-efficient semiconductor solutions.
Posted by employer 4 months ago
First seen on Joblaze 1 month ago
Last verified on the company career page 19 hours ago
Skills & Technologies
Requirements
- Experience
- 8+ years
- Education
- Bachelor's degree
Not disclosed in this posting: compensation, work arrangement, visa sponsorship.
Joblaze summary
In the role of Senior Engineer, FPGA at Ambiq, the individual will focus on developing and debugging FPGA images to support pre-silicon prototyping efforts. Key skills include expertise in RTL design, FPGA prototyping platforms, and familiarity with tools like Xilinx Vivado and Intel Quartus Prime Pro. This position is ideal for seasoned engineers with over six years of experience in SoC design and FPGA development, who thrive in a fast-paced, collaborative environment. Ambiq's commitment to innovation and energy efficiency makes it a compelling place for those looking to make a significant impact.
Joblaze insights
Quick facts
- How much experience is required?
- At least 8 years of relevant experience for this Senior Engineer, FPGA role.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: C, FPGA, Git, I2C, I3C, Intel Quartus Prime Pro.
- What seniority level is this role?
- Ambiq targets senior candidates for this position.
- Is this full-time or contract?
- Full-time for this Senior Engineer, FPGA role at Ambiq.
From the original posting
Company Overview
As the Senior Engineer, FPGA at Ambiq, you will drive the development and rendering of FPGA images in support of our pre-silicon prototyping environments.
In this role, you will work with our SoC design, software development, design verification, and system test teams as our primary internal customers for the FPGA images.
The successful candidate will have experience in RTL design, verification, and FPGA/Prototyping platform creation to support Design Verification, Validation, Software Development and System Test at the pre-silicon phase.
The person in this role must be comfortable working with RTL to implement specialized changes to the SoC database for the FPGA development flow. This role will require defining and implementing internal and external FPGA timing constraints to enable repeated delivery of design iterations to the software and validation teams. The candidate will be required to debug RTL designs using FPGA tools, external logic analyzers, and protocol analyzers.
Responsibilities
- Implement and debug FPGA designs on AMD FPGA based prototyping platforms using Xilinx Vivado and ISE tools.
- Implement and debug FPGA designs on a Stratix-10 development board using Intel Quartus prime Pro.
- Support a regression test-suite consisting of system-level test cases to validate updated FPGA builds.
- Assist development teams in reproduction, triage, and debug of issues both pre-silicon and post-silicon
- Define and implement timing constraints.
Qualifications
- BSEE or BSCE with 6+ years of SoC design, verification, or related work experience and 8+ years of experience of FPGA design, bring-up, debugging, and verification.
- In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on an FPGA development platform.
- Solid experience with defining timing constraints for Static Timing Analysis.
- Some familiarity with Cadence SoC design flow.
- Expertise in both Intel Quartus Prime Pro and Xilinx Vivado suites.
- Solid understanding of the tool flow from RTL to bitstream.
- Some familiarity with programming in C language.
- Familiarity with source code control systems (git) required.
- Familiarity with simulation tools.
- Hands-on lab bring-up experience, debug, and instrument usage.
In addition, the following areas of experience are highly desirable for the position but not strictly required:
- In-depth experience with Stratix 10 FPGA platforms: boards, debug, performance, and throughput tuning.
- In-depth experience with AMD VU19P prototyping systems, debug, design partitioning, performance, and throughput tuning.
- Experience with Siemens proFPGA prototyping/emulation platform and VPS software.
- Experience with ARM’s MPS4 platform.
- Experience with low power designs.
- Experience with embedded microprocessors.
- Proven design validation skills.
- In-depth experience writing Verilog code.
- Experience with System Verilog verification environments.
- Good analytical skills.
- Python script experience.
- YAML
- Peripheral protocols: I2C, I3C, MSPI, UART, USB
Standard company text repeated across Ambiq's postings is omitted here.