← Back to results

Physical Design Engineer

Join Etched as a Physical Design Engineer to optimize block-level implementation and drive PPA improvements in a fast-paced startup environment.

Location
San Jose
Compensation
Not disclosed
Level
senior
Type
full time · On-site

Posted by employer 1 year ago

First seen on Joblaze 3 days ago

Last verified on the company career page 1 day ago

Apply at Etched → Save job Scanned from etched.com

Skills & Technologies

What you'll build

  • Own block-level implementation and verification
  • Drive timing closure and PPA optimization
  • Supervise 3rd party design work
  • Improve design flows and iteration speed
  • Collaborate with RTL Designers

Must have

  • 5-10+ years of previous experience with PD
  • Experience with back-end design and timing closure on advanced process nodes
  • Experience with Cadence or Synopsys automated RTL-to-GDSII flows
  • Experience with sign-off tools
  • Experience with UPF-based low power design methodology

Nice to have

  • Familiarity with modern ML and LLM model architectures
  • Ability to program with Python or another scripting language
  • Familiarity with AI tools for programming/coding
  • Startup experience or comfort working in fast-paced environments

Requirements

Experience
5–10 years

Not disclosed in this posting: compensation, visa sponsorship.

Benefits

Wellness Benefits Daily Meals Housing Subsidy Unlimited Compute Budget Health Insurance Relocation Assistance

Joblaze summary

In the role of Physical Design Engineer at Etched, the individual will manage block-level implementation and verification while optimizing timing closure and performance. Key skills include expertise in physical design tools and methodologies, particularly for advanced process nodes, as well as experience with automated RTL-to-GDSII flows. This position is suited for seasoned professionals with 5-10 years in the field, ideally those who thrive in fast-paced startup environments and possess a creative mindset. Etched emphasizes a collaborative culture where engineering and research intersect, fostering innovation across disciplines.

Joblaze insights

  • Listed 3 days ago — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page September 23, 2026.
  • This exact title is also open at 1 other location at Etched: Austin.
  • Python appears in 52.3% of 545 comparable senior ai/ml roles in United States; Synopsys appears in 0.6% of 545 comparable senior ai/ml roles in United States.

Quick facts

Is the Physical Design Engineer role remote?
No — this is an on-site role in San Jose.
How much experience is required?
5–10 years of relevant experience for this Physical Design Engineer role.
Where is the role based?
Etched is hiring for this position in San Jose.
What's the tech stack?
Joblaze extracted these technologies from the posting: Cadence, Python, Synopsys.
What seniority level is this role?
Etched targets senior candidates for this position.
Is this full-time or contract?
Full-time for this Physical Design Engineer role at Etched.

From the original posting

Job Summary

Etched is looking for exceptional Physical Design engineers to join our team. In this role, you
will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.


Key Responsibilities

  • Deeply understand what is involved in physical design

  • Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,
    improve CAD infrastructure

  • Collaborate with RTL Designers and provide Physical Design feedback to improve PPA

  • Drive dashboards that show the convergence of projects related to PD

  • Optimize tool flows, working with EDA vendors to incorporate the latest features

  • Accountable for block level closure

  • Supervise the outsourcing of physical design to a 3rd party service

  • 5-10+ years of previous experience with PD

  • Tools, flow, and design methodology from RTL synthesis to GDSII sign-off

  • Experience with back-end design and timing closure on advanced process nodes (5nm
    and below)

  • Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)
    automated RTL-to-GDSII flows

  • Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)

  • Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,
    routing, IR drop, and EM/antenna analysis

  • Deeply creative and able to think from first principles

Strong candidates may also have experience with

  • Familiarity with modern ML and LLM model architectures

  • Ability to program with Python or another scripting language

  • Familiarity with AI tools for programming/coding

  • Startup experience or comfort working in fast-paced environments

Benefits

  • Medical, dental, and vision packages with generous premium coverage

    • $500 per month credit for waiving medical benefits

  • Housing subsidy of $2.5k per month for those living within walking distance of the office

  • Daily lunch + dinner in our office

  • Unlimited compute budget subject to ROI justification

 

Standard company text repeated across Etched's postings is omitted here.