Join Etched as a Physical Design Engineer to optimize design flows and collaborate on cutting-edge hardware for frontier intelligence.
Posted by employer 5 months ago
First seen on Joblaze 15 hours ago
Last verified on the company career page 15 hours ago
What you'll build
- Own block-level implementation and verification
- Drive timing closure and PPA optimization
- Supervise 3rd party design work
- Improve design flows and iteration speed
- Collaborate with RTL Designers
Must have
- 5-10+ years of previous experience with PD
- Experience with back-end design and timing closure on advanced process nodes
- Experience with Cadence or Synopsys automated RTL-to-GDSII flows
- Experience with sign-off tools
- Experience with UPF-based low power design methodology
Nice to have
- Familiarity with modern ML and LLM model architectures
- Ability to program with Python or another scripting language
- Familiarity with AI tools for programming/coding
- Startup experience or comfort working in fast-paced environments
Practical constraints
- Regular time spent working alongside the team in San Jose
- Expect to spend approximately two weeks per month at San Jose headquarters initially
Requirements
- Experience
- 5–10 years
Not disclosed in this posting: compensation, visa sponsorship.
Benefits
Joblaze summary
In the role of Physical Design Engineer at Etched, the individual will focus on block-level implementation and verification, ensuring timing closure and optimizing performance, power, and area (PPA). Key skills include expertise in physical design tools and methodologies, particularly for advanced process nodes, as well as experience with automated RTL-to-GDSII flows. This position is suited for seasoned professionals with 5-10 years of relevant experience, ideally from a startup background, who can thrive in a fast-paced environment. Etched emphasizes a collaborative culture where engineering and research intersect, fostering innovation in frontier intelligence hardware.
Joblaze insights
- Listed today — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page September 21, 2026.
- This exact title is also open at 1 other location at Etched: San Jose, United States.
- Python appears in 17% of 2159 comparable senior other roles in United States; Cadence appears in 0.1% of 2159 comparable senior other roles in United States.
Quick facts
- Is the Physical Design Engineer role remote?
- It's hybrid — Etched expects some on-site time in Austin, United States.
- How much experience is required?
- 5–10 years of relevant experience for this Physical Design Engineer role.
- Where is the role based?
- Etched is hiring for this position in Austin, United States.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: Cadence, Python, Synopsys.
- What seniority level is this role?
- Etched targets senior candidates for this position.
- Is this full-time or contract?
- Full-time for this Physical Design Engineer role at Etched.
From the original posting
Job Summary
Etched is looking for exceptional Physical Design engineers to join our team. In this role, you
will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.
Key Responsibilities
Deeply understand what is involved in physical design
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,
improve CAD infrastructureCollaborate with RTL Designers and provide Physical Design feedback to improve PPA
Drive dashboards that show the convergence of projects related to PD
Optimize tool flows, working with EDA vendors to incorporate the latest features
Accountable for block level closure
Supervise the outsourcing of physical design to a 3rd party service
You may be a good fit if you have
5-10+ years of previous experience with PD
Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
Experience with back-end design and timing closure on advanced process nodes (5nm
and below)Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)
automated RTL-to-GDSII flowsExperience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,
routing, IR drop, and EM/antenna analysisDeeply creative and able to think from first principles
Strong candidates may also have experience with
Familiarity with modern ML and LLM model architectures
Ability to program with Python or another scripting language
Familiarity with AI tools for programming/coding
Startup experience or comfort working in fast-paced environments
Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Daily lunch + dinner in our office
Unlimited compute budget subject to ROI justification
We greatly value engineering skills. We do not have strict boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.
Standard company text repeated across Etched's postings is omitted here.