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Physical Design Engineer - Block Level, Subsystem Implementation

Own block-level implementation from synthesis through GDSII sign-off as a Physical Design Engineer at a cutting-edge AI hardware startup.

Location
San Jose, United States
Compensation
Not disclosed
Level
senior
Type
full time · On-site

Posted by employer 2 months ago

First seen on Joblaze 1 day ago

Last verified on the company career page 1 day ago

Apply at Etched → Save job Scanned from etched.com

Skills & Technologies

What you'll build

  • Own block-level and/or subsystem physical design end to end
  • Drive block-level timing closure
  • Close block-level signoff across EM, IR drop, RC extraction
  • Generate abstracts, views, and timing budgets
  • Supervise physical design work outsourced to 3rd party services

Must have

  • 5-10+ years of previous experience with PD
  • Experience with back-end design and timing closure on advanced process nodes
  • Experience with Cadence or Synopsys automated RTL-to-GDSII flows
  • Experience with sign-off tools
  • Scripting ability in Tcl, Python, or Perl

Nice to have

  • Familiarity with modern ML and LLM model architectures
  • Ability to program with Python or another scripting language
  • Familiarity with AI tools for programming/coding
  • Startup experience or comfort working in fast-paced environments

Requirements

Experience
5–10 years

Not disclosed in this posting: compensation, visa sponsorship.

Benefits

Wellness Benefits Daily Meals Housing Subsidy Unlimited Compute Budget Health Insurance Relocation Assistance

Joblaze summary

In the role of Physical Design Engineer at Etched, the individual will manage block-level implementation tasks, including synthesis and GDSII sign-off, while optimizing performance, power, and area (PPA). Proficiency in tools like Cadence and Synopsys, along with experience in back-end design on advanced process nodes, is essential. This position is suited for seasoned professionals with 5-10 years of relevant experience, particularly those comfortable in fast-paced startup environments. Etched emphasizes a collaborative culture where engineering and research intersect, fostering innovation in AI hardware.

Joblaze insights

  • Listed yesterday — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page September 21, 2026.
  • This exact title is also open at 1 other location at Etched: Austin, United States.
  • Python appears in 52.7% of 535 comparable senior ai/ml roles in United States; Perl appears in 0.4% of 535 comparable senior ai/ml roles in United States.

Quick facts

Is the Physical Design Engineer - Block Level, Subsystem Implementation role remote?
No — this is an on-site role in San Jose, United States.
How much experience is required?
5–10 years of relevant experience for this Physical Design Engineer - Block Level, Subsystem Implementation role.
Where is the role based?
Etched is hiring for this position in San Jose, United States.
What's the tech stack?
Joblaze extracted these technologies from the posting: Cadence, Perl, Python, Synopsys, TCL.
What seniority level is this role?
Etched targets senior candidates for this position.
Is this full-time or contract?
Full-time for this Physical Design Engineer - Block Level, Subsystem Implementation role at Etched.

From the original posting

Job Summary

Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off. You will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.

Key Responsibilities

  • Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII.

  • Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation.

  • Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna).

  • Generate abstracts, views, and timing budgets for clean hierarchical integration of your blocks into the top level.

  • Collaborate with RTL Designers and provide Physical Design feedback to improve PPA.

  • Continuously improve the PPA of owned blocks and contribute learnings back into the shared RTL-to-GDSII flow.

  • Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks.

You may be a good fit if you have

  • 5-10+ years of previous experience with PD

  • Tools, flow, and design methodology from RTL synthesis to GDSII sign-off

  • Experience with back-end design and timing closure on advanced process nodes (5nm and below)

  • Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows

  • Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)

  • Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis

  • Scripting ability in Tcl, Python, or Perl for flow automation and debug

  • Deeply creative and able to think from first principles

Strong candidates may also have experience with

  • Familiarity with modern ML and LLM model architectures

  • Ability to program with Python or another scripting language

  • Familiarity with AI tools for programming/coding

  • Startup experience or comfort working in fast-paced environments


Benefits

  • Medical, dental, and vision packages with generous premium coverage

    • $500 per month credit for waiving medical benefits

  • Housing subsidy of $2.5k per month for those living within walking distance of the office

  • Daily lunch and dinner in our office

  • Unlimited compute budget subject to ROI justification

 

Standard company text repeated across Etched's postings is omitted here.

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