Joblaze summary

The Design Verification Engineer at Etched focuses on ensuring the reliability and performance of custom IPs that drive their advanced chip designs. This role requires expertise in UVM and SystemVerilog, along with strong debugging skills to address complex digital design challenges. Ideal candidates are experienced engineers with a solid foundation in computer architecture and digital design, particularly those familiar with high-throughput systems like systolic arrays and DMA engines. Etched fosters a collaborative environment where technical staff engage across engineering and research disciplines.

Joblaze insights

Listed about a month ago — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page November 8, 2026.
This exact title is also open at 1 other location at Etched: Austin.
Python appears in 17.8% of 3490 comparable mid other roles in United States; TCL appears in 0.3% of 3490 comparable mid other roles in United States.

Quick facts

Is the Design Verification Engineer - Internal IP role remote?: No — this is an on-site role in San Jose.
Where is the role based?: Etched is hiring for this position in San Jose.
What's the tech stack?: Joblaze extracted these technologies from the posting: Perl, Python, SystemVerilog, TCL, UVM.
What seniority level is this role?: Etched targets mid-level candidates for this position.
Is this full-time or contract?: Full-time for this Design Verification Engineer - Internal IP role at Etched.

From the original posting

Job Summary

We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Key responsibilities

Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
Debug complex datapath and protocol issues in RTL and testbench environments.
Work closely with architects and designers to validate functionality and design intent.
Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

Proficiency with UVM and SystemVerilog.
Strong debugging and problem-solving skills for complex digital designs.
Solid knowledge of computer architecture and digital design fundamentals.
Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

Strong candidates may also have experience with

Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.
Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.

Benefits

Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
Housing subsidy of $2.5k per month for those living within walking distance of the office
Daily lunch + dinner in our office
Unlimited compute budget subject to ROI justification

Standard company text repeated across Etched's postings is omitted here.

Design Verification Engineer - Internal IP

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