Join Etched as a Physical Design Engineer to lead block-level implementation for cutting-edge AI hardware.
Posted by employer 1 month ago
First seen on Joblaze 2 days ago
Last verified on the company career page 2 hours ago
What you'll build
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Requirements
Not disclosed in this posting: compensation, visa sponsorship.
Benefits
Joblaze summary
In the role of Physical Design Engineer at Etched, the individual will manage block-level implementation tasks, overseeing the entire process from synthesis to GDSII sign-off. Key skills include expertise in back-end design, timing closure, and familiarity with tools like Cadence and Synopsys, particularly for advanced process nodes. This position is suited for experienced engineers with 5-10 years in physical design, ideally those who thrive in fast-paced environments and possess a creative mindset. Etched emphasizes a collaborative culture where engineering and research intersect, fostering innovation in AI hardware.
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From the original posting
Job Summary
Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off. You will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.
Key Responsibilities
Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII.
Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation.
Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna).
Generate abstracts, views, and timing budgets for clean hierarchical integration of your blocks into the top level.
Collaborate with RTL Designers and provide Physical Design feedback to improve PPA.
Continuously improve the PPA of owned blocks and contribute learnings back into the shared RTL-to-GDSII flow.
Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks.
5-10+ years of previous experience with PD
Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
Experience with back-end design and timing closure on advanced process nodes (5nm and below)
Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
Scripting ability in Tcl, Python, or Perl for flow automation and debug
Deeply creative and able to think from first principles
Strong candidates may also have experience with
Familiarity with modern ML and LLM model architectures
Ability to program with Python or another scripting language
Familiarity with AI tools for programming/coding
Startup experience or comfort working in fast-paced environments
Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Daily lunch and dinner in our office
Unlimited compute budget subject to ROI justification
We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.
Standard company text repeated across Etched's postings is omitted here.