Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.
Posted by employer 5 months ago
First seen on Joblaze 21 hours ago
Last verified on the company career page 21 hours ago
Skills & Technologies
What you'll build
- Develop and maintain UVM/SystemVerilog testbenches
- Define and execute verification plans
- Debug complex datapath and protocol issues
- Validate functionality and design intent
- Contribute to reusable DV infrastructure
Must have
- Proficiency with UVM and SystemVerilog
- Strong debugging and problem-solving skills
- Solid knowledge of computer architecture
- Hands-on experience verifying datapaths
Nice to have
- Familiarity with SystemVerilog Assertions
- Experience verifying systolic arrays
- Scripting skills for automation
Practical constraints
- Regular time spent working in San Jose
- Expect to spend approximately two weeks per month at San Jose headquarters
Not disclosed in this posting: compensation, years of experience, visa sponsorship.
Benefits
Joblaze summary
The Design Verification Engineer at Etched focuses on ensuring the reliability and performance of custom IPs that drive their advanced chip designs. This role requires expertise in UVM and SystemVerilog, along with strong debugging skills to address complex digital design challenges. Ideal candidates will have a background in computer architecture and experience with high-throughput fabrics, making this position suitable for engineers looking to deepen their verification skills in a cutting-edge environment. The team emphasizes collaboration across disciplines, reflecting Etched's commitment to integrating engineering and research.
Joblaze insights
- Listed today — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page September 21, 2026.
- This exact title is also open at 1 other location at Etched: San Jose, United States.
- Python appears in 17.9% of 2881 comparable mid other roles in United States; UVM appears in 0.3% of 2881 comparable mid other roles in United States.
Quick facts
- Is the Design Verification Engineer - Internal IP role remote?
- It's hybrid — Etched expects some on-site time in Austin, United States.
- Where is the role based?
- Etched is hiring for this position in Austin, United States.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: Perl, Python, SystemVerilog, TCL, UVM.
- What seniority level is this role?
- Etched targets mid-level candidates for this position.
- Is this full-time or contract?
- Full-time for this Design Verification Engineer - Internal IP role at Etched.
From the original posting
Job Summary
We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.
Key responsibilities
Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
Debug complex datapath and protocol issues in RTL and testbench environments.
Work closely with architects and designers to validate functionality and design intent.
Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
Contribute to reusable DV infrastructure, coverage models, and methodology improvements.
You may be a good fit if you have
Proficiency with UVM and SystemVerilog.
Strong debugging and problem-solving skills for complex digital designs.
Solid knowledge of computer architecture and digital design fundamentals.
Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
Strong candidates may also have experience with
Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.
Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.
Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Daily lunch + dinner in our office
Unlimited compute budget subject to ROI justification
We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.
Standard company text repeated across Etched's postings is omitted here.
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