How much experience is required?

At least 1 year of relevant experience for this Physical Design Engineer (Silicon Engineering) role.

What's the tech stack?

Joblaze extracted these technologies from the posting: ASIC, CMOS, EDA tools, FinFET, Perl, Python.

Does SpaceX sponsor work visas for this role?

Yes — the posting indicates visa sponsorship is available for the right candidate.

What seniority level is this role?

SpaceX targets mid-level candidates for this position.

Is this full-time or contract?

Full-time for this Physical Design Engineer (Silicon Engineering) role at SpaceX.

Physical Design Engineer (Silicon Engineering) at SpaceX

Joblaze summary

The Physical Design Engineer at SpaceX focuses on developing next-generation ASICs for both space and ground infrastructures, ensuring the performance and reliability of the Starlink network. Key skills include expertise in physical design methodologies, familiarity with EDA tools, and a solid understanding of CMOS principles. This role is suited for engineers with at least one year of experience in RTL to GDSII design, particularly those who thrive in collaborative, fast-paced environments. The position offers the chance to work on innovative projects that have a significant global impact.

Joblaze insights

Listed today on Joblaze — tracked directly from SpaceX's career page.
SpaceX has 2449 other open roles including Avionics Systems Engineer (Starship), Battery Engineer (Falcon & Dragon), Avionics Wire Harness Technician (Starship).
6527 active Python roles on Joblaze right now.
434 active bash roles on Joblaze right now.
86 active Perl roles on Joblaze right now.
Typical Python salary we track runs $125,000–$190,800 (median $160,000, across 3229 roles). See Python salary trends

Quick facts

How much experience is required?: At least 1 year of relevant experience for this Physical Design Engineer (Silicon Engineering) role.
What's the tech stack?: Joblaze extracted these technologies from the posting: ASIC, CMOS, EDA tools, FinFET, Perl, Python.
Does SpaceX sponsor work visas for this role?: Yes — the posting indicates visa sponsorship is available for the right candidate.
What seniority level is this role?: SpaceX targets mid-level candidates for this position.
Is this full-time or contract?: Full-time for this Physical Design Engineer (Silicon Engineering) role at SpaceX.

From the original posting

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
Develop/improve physical design methodologies and automation scripts for various implementation steps
Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

Bachelor’s degree in electrical engineering, computer engineering or computer science
1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
Knowledge of deep sub-micron FinFET and CMOS solid state physics
Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
Familiar with CMOS analog circuit and physical design
Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

Ability to work extended hours and weekends as needed to meet critical project milestones

ITAR REQUIREMENTS:

To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

Physical Design Engineer (Silicon Engineering)

Similar positions