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Physical Design Engineer (Silicon Engineering)

Join SpaceX as a Physical Design Engineer to develop next-generation ASICs for the Starlink network.

Location
Irvine, CA
Compensation
$125k–$195k/yr
Level
mid
Type
full time

Posted by employer 1 month ago

First seen on Joblaze 1 month ago

Last verified on the company career page 22 hours ago

What you'll build

  • Perform partition synthesis and physical implementation steps
  • Develop/improve physical design methodologies and automation scripts
  • Collaborate with the ASIC design team
  • Resolve design/timing/congestion and flow issues
  • Run, debug, and fix signoff closure issues

Must have

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 1+ years of professional experience working on RTL2GDSII physical design

Nice to have

  • Experience with industry standard EDA tools
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Understanding of CMOS digital design principles
  • Familiar with CMOS analog circuit and physical design
  • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile)

Practical constraints

  • Ability to work extended hours and weekends as needed

Requirements

Experience
1+ years
Education
Bachelor's degree
Visa
Sponsorship available

Not disclosed in this posting: work arrangement.

Benefits

401k Match Paid Vacation Equity/Stock Options Paid Holidays Health Insurance Parental Leave

Joblaze summary

In the role of Physical Design Engineer at SpaceX, the engineer will focus on developing next-generation ASICs for both space and ground infrastructures, ensuring optimal performance and connectivity for the Starlink network. Key skills include expertise in physical design methodologies, familiarity with EDA tools, and a solid understanding of CMOS principles. This position is suited for individuals with at least one year of relevant experience, particularly those who thrive in collaborative, fast-paced environments. The team is dedicated to pushing the boundaries of satellite technology and connectivity.

Joblaze insights

  • Listed about a month ago — first seen on Joblaze September 12, 2026. Last confirmed on SpaceX's careers page October 31, 2026.
  • This exact title is also open at 2 other locations at SpaceX: Austin, TX, Palo Alto, CA.
  • Salary band is in line with the typical range for comparable tech roles (median ~$128,800).
  • Starts above 63% of 345 comparable mid other roles in United States that list Python we track (median $111,197 across 63 companies). See Python salary trends
  • Python appears in 18% of 3361 comparable mid other roles in United States; EDA tools appears in 0.1% of 3361 comparable mid other roles in United States.

Quick facts

What's the salary range?
SpaceX lists $125,000–$195,000 for this role.
How much experience is required?
At least 1 year of relevant experience for this Physical Design Engineer (Silicon Engineering) role.
What's the tech stack?
Joblaze extracted these technologies from the posting: ASIC, CMOS, EDA tools, FinFET, Makefile, Perl.
Does SpaceX sponsor work visas for this role?
Yes — the posting indicates visa sponsorship is available for the right candidate.
What seniority level is this role?
SpaceX targets mid-level candidates for this position.
Is this full-time or contract?
Full-time for this Physical Design Engineer (Silicon Engineering) role at SpaceX.

From the original posting

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

PREFERRED SKILLS AND EXPERIENCE:

  • Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
  • Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
  • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:

  • Ability to work extended hours and weekends as needed to meet critical project milestones
COMPENSATION AND BENEFITS:

Pay Range:
Level 1: $125,000.00 - $160,000.00
Level 2: $145,000.00 - $195,000.00

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

ITAR REQUIREMENTS:

Standard company text repeated across SpaceX's postings is omitted here.

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