"chip level packaging" Jobs
276 open tech roles matching “chip level packaging”, taken straight from company career pages — not reposted from other job boards. Every listing is re-checked daily and closed roles are removed.
Showing 20 of 276 results
Join Graphcore as a Silicon Physical Design Engineer to work on cutting-edge AI superchips in a collaborative environment.
Own the end-to-end execution of custom silicon for AI systems at Anthropic, driving external partnerships and program management.
Join SpaceX as a CNC Machinist to operate advanced machinery and produce critical flight hardware for Starship components.
Design and test critical electronics for high-power satellites at a fast-paced, high-growth company.
Join K2 Space as a Senior Mixed-Signal Post-Silicon Validation Engineer to validate and characterize complex mixed-signal SoCs.
Join SpaceX as a Piping Technician to support the Starlink User Terminal Production Facility in a fast-paced manufacturing environment.
Lead power engineering efforts at Graphcore, a leader in AI computing systems, in a hybrid role based in Milpitas, CA.
Join SpaceX as a Sr. ASIC Design Engineer to develop cutting-edge ASICs for the Starlink network.
Design and test critical electronics for high-power satellites at a fast-paced, high-growth company.
Lead the end-to-end returns and repair operation for AI hardware at a rapidly scaling startup.
Join SpaceX as an ASIC Design Engineer to develop cutting-edge FPGAs and ASICs for the Starlink broadband internet system.
Join IonQ as a Senior Photonics Test Engineer to develop and optimize testing infrastructure for advanced quantum computing technologies.
Join SpaceX as an RF/Microwave Engineer to develop next-generation RFICs for the Starlink network, enhancing global connectivity.
Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.
Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.
Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.