"questa" Jobs

12 open tech roles matching “questa”, taken straight from company career pages — not reposted from other job boards. Every listing is re-checked daily and closed roles are removed.

No "questa" jobs in Berlin right now — showing "questa" jobs in all locations.

Showing 12 of 12 results

Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 6 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 1 week ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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FPGA/ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an FPGA/ASIC Design Engineer to develop cutting-edge chips for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 1 week ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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Manager, ASIC Design Engineering (Starshield Silicon) Visa

SpaceX Hawthorne, CA $190k–$245k/yr Published 5 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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ASIC Design Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC Design Engineer to develop cutting-edge FPGAs and ASICs for the Starlink broadband internet system.

SpaceX Palo Alto, CA $135k–$175k/yr Published 4 days ago

C++ Xilinx Vivado Verilog DSP HDL simulators

Flexible on stack

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Formal Verification - DV

Join Etched as a Formal Verification Engineer to drive verification strategies for complex ASIC designs in a fast-paced startup environment.

Etched San Jose Published 4 months ago

SystemVerilog Assertions Synopsys VC Formal Siemens Questa Formal SystemVerilog Cadence JasperGold

Flexible on stack

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 6 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Applications Engineer Hybrid

Join ChipAgents as an Applications Engineer to guide enterprise customers in deploying AI-driven chip design solutions.

ChipAgents San Jose $130k–$350k/yr Published 4 months ago

lint Verilog CDC shell scripting Python

Flexible on stack

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Principal ASIC Design Verification Engineer

Join K2 Space as a Principal ASIC Design Verification Engineer to shape first-generation silicon in a high-growth environment.

K2 Space United States - Remote $190k–$285k/yr Published 3 months ago

C++ Python UVM Perl TCL

Flexible on stack

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Senior ASIC Design Verification Engineer

Join K2 Space as a Senior ASIC Design Verification Engineer to shape first-generation silicon in a fast-paced, high-growth environment.

K2 Space United States - Remote $170k–$250k/yr Published 3 months ago

Python UVM Perl TCL SystemVerilog

Flexible on stack

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Principal ASIC Design Verification Engineer

Join K2 Space as a Principal ASIC Design Verification Engineer to shape first-generation silicon in a fast-paced, high-growth environment.

K2 Space Seattle, WA $190k–$285k/yr Published 3 months ago

C++ Python UVM Perl TCL

Flexible on stack

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Senior ASIC Design Verification Engineer

Join K2 Space as a Senior ASIC Design Verification Engineer to shape first-generation silicon in a fast-paced, high-growth environment.

K2 Space Seattle, WA $170k–$250k/yr Published 3 months ago

Python UVM Perl TCL SystemVerilog

Flexible on stack

Apply →