"digital asic design" Jobs

15 open tech roles matching “digital asic design”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: ASIC, Python, PCB. Every listing is re-checked daily and closed roles are removed.

Showing 15 of 15 results

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Palo Alto, CA $155k–$185k/yr Published 3 months ago

FinFET EDA Makefile ASIC Python

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Palo Alto, CA $170k–$230k/yr Published 2 months ago

FinFET bash ASIC Python Perl

Flexible on stack

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

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New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering, working on next-gen silicon for the Starlink program.

SpaceX Palo Alto, CA $135k–$175k/yr Published 1 week ago

ADS Verilog HFSS RTL Momentum

Flexible on stack

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Sr. DSP Systems Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. DSP Systems Engineer to develop cutting-edge ASICs for satellite broadband systems.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 week ago

C++ RF MIMO FPGA ASIC

Flexible on stack

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Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

Filters vector modulators low noise amplifiers Mixed-Signal Spread Spectrum

Flexible on stack

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Sr. Technical Project Lead (Silicon Engineering) Visa

Lead complex silicon projects at SpaceX, developing next-generation ASICs for Starlink's global connectivity solutions.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

Project Management Digital ASIC Design Silicon Engineering PCB FPGA

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Electrical Design Engineer, Satellites Payload (Starlink) Visa

Join SpaceX as an Electrical Design Engineer to develop high-reliability electronics for the Starlink satellite communication network.

SpaceX Palo Alto, CA $115k–$185k/yr Published 2 weeks ago

C++ RF PAM4 PCB Physics

Flexible on stack

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Sr. Hardware Design Engineer - Electrical, Satellites Payload (Starlink) Visa

Join SpaceX as a Sr. Hardware Design Engineer to develop high-reliability electronics for the Starlink satellite communication network.

SpaceX Palo Alto, CA Published 1 month ago

C++ RF PAM4 PCB Physics

Flexible on stack

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Sr. Electrical Design Engineer, Satellites Payload (Starlink) Visa

Join SpaceX as a Sr. Electrical Design Engineer to develop high-reliability electronics for the Starlink satellite communication network.

SpaceX Palo Alto, CA Published 1 month ago

C++ RF PAM4 PCB Physics

Flexible on stack

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Signal Integrity Engineer - Serdes, Satellites (Starlink) Visa

Join SpaceX as a Signal Integrity Engineer to drive the design and troubleshooting of advanced satellite hardware for Starlink.

SpaceX Palo Alto, CA $115k–$155k/yr Published 1 week ago

Thermal Engineering PCB DSP RF engineering C/C++

Flexible on stack

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Sr. SI/PI Engineer - Serdes, Satellites (Starlink) Visa

Join SpaceX as a Sr. SI/PI Engineer to lead signal and power integrity efforts for advanced satellite hardware in the Starlink project.

SpaceX Palo Alto, CA Published 1 month ago

C++ PCB DSP FPGA ASIC

Flexible on stack

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Sr. Signal Integrity Engineer - Serdes, Satellites (Starlink) Visa

Join SpaceX as a Sr. Signal and Power Integrity Engineer to drive the development of advanced satellite hardware for Starlink.

SpaceX Palo Alto, CA Published 1 month ago

Thermal Engineering Power integrity PCB DSP RF engineering

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