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"systemverilog assertions" Jobs

2 open tech roles matching “systemverilog assertions”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: SystemVerilog, Synopsys VC Formal, Python. Every listing is re-checked daily and closed roles are removed.

Showing 2 of 2 results

Etched
Formal Verification - DV

Join Etched as a Formal Verification Engineer to drive verification strategies for complex ASIC designs in a fast-paced startup environment.

Etched San Jose Published 3 months ago
SystemVerilog Assertions Synopsys VC Formal Siemens Questa Formal SystemVerilog Cadence JasperGold
Flexible on stack
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Etched
Design Verification Engineer - Internal IP

Join Etched as a Design Verification Engineer to ensure high-performance custom IPs for cutting-edge AI hardware.

Etched San Jose Published 1 year ago
Python UVM Perl TCL SystemVerilog
Flexible on stack
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