"rtl" Jobs - Joblaze

Showing 11 of 11 results

Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Sunnyvale, CA $170k–$235k/yr Published 1 week ago

Verilog ASIC Python System Verilog SoC

Flexible on stack

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Principal DFT Engineer (Silicon Engineering) Visa

SpaceX Sunnyvale, CA $210k–$295k/yr Published 3 months ago

C++ Verilog Siemens Tessent UPF RTL

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Lead RTL Design Engineer Remote

Cerebras Systems Sunnyvale, CA $175k–$275k/yr Published 6 months ago

PCIe RDMA RTL ASIC Python

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3D Physical Design Engineer

Cerebras Systems Sunnyvale, CA $150k–$270k/yr Published 1 year ago

AI/ML Calibre ICV Python TCL

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Sunnyvale, CA $135k–$180k/yr Published 1 week ago

Python UVM SystemVerilog MATLAB

Flexible on stack

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Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Sunnyvale, CA $170k–$240k/yr Published 1 week ago

ASIC VMM Python UVM OVM

Flexible on stack

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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for space and ground infrastructures.

SpaceX Sunnyvale, CA $170k–$230k/yr Published 4 days ago

FinFET bash ASIC Python Perl

Flexible on stack

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Design Verification Engineer Remote

Cerebras Systems Sunnyvale, CA $120k–$240k/yr Published 6 months ago

Python UVM Perl SystemVerilog

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Physical Design Engineer II (Silicon Engineering) Visa

SpaceX Sunnyvale, CA $155k–$185k/yr Published 4 weeks ago

FinFET EDA Makefile ASIC Python

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AI Silicon Physical Design Engineer

Cerebras Systems Remote, California, United States; Sunnyvale, CA $150k–$250k/yr Published 1 year ago

Design Compiler ICC2 AI/ML Calibre ICV

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Sunnyvale, CA $210k–$310k/yr Published 1 week ago

FPGA ASIC VMM Python UVM

Flexible on stack

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