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SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Sunnyvale, CA $170k–$235k/yr Published 1 week ago
Verilog ASIC Python System Verilog SoC
Flexible on stack
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Cerebras Systems
Senior/Staff Engineer : Post Silicon- Bring Up Remote
Cerebras Systems Bengaluru, Karnataka, India; Sunnyvale, CA; Toronto, Ontario, Canada $175k–$275k/yr Published 3 months ago
C++ Verilog CI/CD Git AI/ML
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SpaceX
Principal DFT Engineer (Silicon Engineering) Visa
SpaceX Sunnyvale, CA $210k–$295k/yr Published 3 months ago
C++ Verilog Siemens Tessent UPF RTL
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Cerebras Systems
Senior/Staff- Engineer: Post Silicon- Bring Up Remote
Cerebras Systems Bengaluru, Karnataka, India; Sunnyvale, CA; Toronto, Ontario, Canada $175k–$275k/yr Published 3 months ago
C++ Verilog CI/CD Git Python
Apply →

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