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Senior System Verilog Jobs

6 open positions · Updated 1 week ago

Average salary (USD/year): 162.5k–227.5k/yr
6 roles Senior 6 5–8 yrs experience Austin, TX +5 more Full-time newest 1 week ago
Also hiring: Python Verilog ASIC SoC Xilinx Vivado AHB

Showing 6 of 6 positions

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Ambiq
Senior Engineer, FPGA

Drive the development of FPGA images for pre-silicon prototyping at Ambiq, focusing on energy-efficient semiconductor solutions.

Ambiq Singapore Published 2 months ago
C++ Xilinx Vivado MSPI Verilog USB
Flexible on stack
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SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $170k–$235k/yr Published 3 months ago
Verilog ASIC Python System Verilog SoC
Flexible on stack
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SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $160k–$225k/yr Published 3 months ago
Verilog ASIC Python System Verilog SoC
Flexible on stack
Apply →
SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. RTL Design Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $160k–$225k/yr Published 3 months ago
Verilog ASIC Python System Verilog SoC
Flexible on stack
Apply →
SpaceX
Sr. RTL Design Engineer (Silicon Engineering) Visa
SpaceX Austin, TX Published 6 months ago
Verilog AHB ASIC Python System Verilog
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SpaceX
Sr. ASIC Design Engineer (Starshield)
SpaceX Hawthorne, CA $160k–$225k/yr Published 5 months ago
Xilinx Vivado Verilog IES Altera Quartus II Spyglass
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