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Principal DFT Engineer (Silicon Engineering)

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

Location
Palo Alto, CA
Compensation
$220k–$355k/yr
Level
principal
Type
full time

Posted by employer 2 months ago

First seen on Joblaze 2 months ago

Last verified on the company career page 22 hours ago

Requirements

Experience
10+ years
Education
Bachelor's degree
Visa
Sponsorship available

Not disclosed in this posting: work arrangement.

Benefits

401k Match Paid Vacation Paid Sick Leave Equity/Stock Options Paid Holidays Health Insurance Parental Leave

Joblaze summary

The Principal DFT Engineer at SpaceX plays a crucial role in developing and optimizing Design for Test (DFT) architectures for next-generation ASICs used in the Starlink network. This position requires extensive experience with ASICs, scan insertion, and DFT methodologies, along with proficiency in programming languages like Perl and Python. Ideal candidates are seasoned engineers with a strong background in RTL design and a knack for solving complex technical challenges. The role involves collaboration with cross-disciplinary teams, contributing to innovative solutions that enhance global connectivity.

Joblaze insights

  • Listed about 2 months ago — first seen on Joblaze August 1, 2026. Last confirmed on SpaceX's careers page October 9, 2026.
  • This exact title is also open at 2 other locations at SpaceX: Austin, TX, Irvine, CA.
  • Salary band is above the typical range for comparable tech roles (median ~$129,582).
  • Starts above 93% of 30 comparable principal other roles in United States that list Python we track (median $200,000 across 8 companies). See Python salary trends
  • Python appears in 21.3% of 188 comparable principal other roles in United States; Perl appears in 1.1% of 188 comparable principal other roles in United States.

Quick facts

What's the salary range?
SpaceX lists $220,000–$355,000 for this role.
How much experience is required?
At least 10 years of relevant experience for this Principal DFT Engineer (Silicon Engineering) role.
What's the tech stack?
Joblaze extracted these technologies from the posting: ASIC, C++, DFT, Perl, Python, Siemens Tessent.
Does SpaceX sponsor work visas for this role?
Yes — the posting indicates visa sponsorship is available for the right candidate.
What seniority level is this role?
SpaceX targets principal-level candidates for this position.
Is this full-time or contract?
Full-time for this Principal DFT Engineer (Silicon Engineering) role at SpaceX.

From the original posting

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

PRINCIPAL DFT ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

  • Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
  • Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
  • Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
  • Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
  • Run and debug non-timing and SDF annotated gate level simulations
  • Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+

BASIC QUALIFICATIONS:

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 10+ years of experience working with ASICs
  • 10+ years of experience in scan insertion and DFT setup, integration and validation

PREFERRED SKILLS AND EXPERIENCE:

  • Leadership experience driving SOC DFT execution from concept through tapeout and product deployment
  • RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT
  • Ability to solve complex problems including clock domain crossings and power optimization
  • Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
  • Familiar with advanced silicon process and technology nodes for high speed and low power consumption
  • Strong implementation or integration of design blocks using Verilog/SystemVerilog
  • Experience working with ATE testers and test teams

ADDITIONAL REQUIREMENTS:

  • Ability to work extended hours and weekends as needed to meet critical milestones
COMPENSATION AND BENEFITS:

Pay Range:
Level 3: $220,000.00 - $355,000.00

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

ITAR REQUIREMENTS:

Standard company text repeated across SpaceX's postings is omitted here.

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