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Senior Vivado Jobs

1 open positions · Updated 1 month ago

1 role Senior 1 5 yrs experience San Francisco Full-time newest 1 month ago

Also hiring: C C++ DSP FPGA SystemVerilog TCL

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Senior FPGA Engineer Visa

Join Astranis as a Senior FPGA Engineer to design and verify RTL for advanced satellite systems.

Astranis San Francisco $175k–$240k/yr Published 2 years ago

C++ Verilog C DSP Vivado

Flexible on stack

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