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Systemverilog Jobs in Irvine

4 open positions · Updated 4 weeks ago

Average salary (USD/year): 146.3k–217.5k/yr
4 roles Mid 2, Junior 1, Principal 1 1–10 yrs experience Irvine, CA Full-time newest 4 weeks ago
Also hiring: Python Verilog ASIC VHDL ADS AHB

Showing 4 of 4 positions

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SpaceX
New Graduate Engineer, Silicon Engineering Visa

Join SpaceX as a New Graduate Engineer in Silicon Engineering to develop next-generation silicon for the Starlink program.

SpaceX Irvine, CA $125k–$160k/yr Published 4 weeks ago
ADS Verilog HFSS RTL Momentum
Flexible on stack
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SpaceX
Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$340k/yr Published 1 month ago
C++ Verilog Siemens Tessent DFT ASIC
Flexible on stack
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SpaceX
Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 2 months ago
Python UVM SystemVerilog MATLAB
Flexible on stack
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SpaceX
RTL Design Engineer (Silicon Engineering) Visa
SpaceX Irvine, CA $125k–$175k/yr Published 5 months ago
APB Verilog AHB DSP Python
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