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Systemverilog Jobs in Irvine

4 open positions · Updated 1 month ago

Average salary: 152.5k–215k/yr

Showing 4 of 4 positions

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Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$175k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

RTL Design Engineer (Silicon Engineering) Visa

SpaceX Irvine, CA $125k–$175k/yr Published 3 months ago

APB Verilog AHB DSP Python

Principal ASIC Design Verification Engineer (Starshield) Visa

SpaceX Irvine, CA $200k–$285k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

Sr. ASIC Design Verification Engineer (Starshield) Visa

SpaceX Irvine, CA $160k–$225k/yr Published 2 months ago

Python UVM SystemVerilog MATLAB

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