Joblaze summary

The Design Verification Engineer at Etched plays a crucial role in ensuring the performance and reliability of custom IPs for their advanced chip designs. This position requires expertise in digital design, RTL, and ASIC flows, with a strong emphasis on performance verification using SystemVerilog and Python. Ideal candidates will have a solid background in performance modeling and debugging, making this role suitable for experienced engineers looking to tackle complex verification challenges. Etched fosters a collaborative environment where engineering and research intersect, emphasizing hands-on contributions across disciplines.

Joblaze insights

Listed about a month ago — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page November 6, 2026.
This exact title is also open at 1 other location at Etched: Austin.
Python appears in 17.9% of 3358 comparable mid other roles in United States; SystemVerilog appears in 0.5% of 3358 comparable mid other roles in United States.

Quick facts

Is the Design Verification Engineer - SoC role remote?: No — this is an on-site role in San Jose.
Where is the role based?: Etched is hiring for this position in San Jose.
What's the tech stack?: Joblaze extracted these technologies from the posting: Python, SystemVerilog.
What seniority level is this role?: Etched targets mid-level candidates for this position.
Is this full-time or contract?: Full-time for this Design Verification Engineer - SoC role at Etched.

From the original posting

Job Summary

We are seeking a Design Verification Engineer to join our Systems/Performance Verification team. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Key responsibilities

Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
Work closely with software and application developers on identifying performance bottlenecks and tuning the software.
Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification.
Improve and maintain the architectural performance models.
Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model.
Develop SystemVerilog or Python-based checkers for verifying the performance features.
Develop coverage monitors and analyze coverage to ensure all performance features are covered.
Debug performance issues and conduct performance tuning on silicon.
Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle.

You may be a good fit if you have

Strong understanding of digital design, RTL, and ASIC design flows.
Hands-on experience with performance verification, simulation, and modeling.
Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.
Skilled in writing Python scripts for automation, data analysis, and performance modeling.
Experience building and maintaining performance models for chip subsystems.
Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators.
Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning
Some exposure to kernel level performance metrics and profiling tools.

Benefits

Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
Housing subsidy of $2.5k per month for those living within walking distance of the office
Daily lunch + dinner in our office
Unlimited compute budget subject to ROI justification

Standard company text repeated across Etched's postings is omitted here.

Design Verification Engineer - SoC

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