Joblaze summary

The Design Verification Engineer at Etched is responsible for ensuring the correctness and performance of various IP subsystems, including PCIe and Ethernet, by developing and maintaining verification environments. This role requires expertise in SystemVerilog and UVM, along with a strong understanding of standard IP interfaces and protocols. Ideal candidates have over five years of design verification experience and thrive in a fast-paced startup environment, collaborating across teams to tackle complex challenges. Etched emphasizes a hands-on approach, blending engineering and research without strict boundaries.

Joblaze insights

Listed about a month ago — first seen on Joblaze September 21, 2026. Last confirmed on Etched's careers page November 8, 2026.
This exact title is also open at 1 other location at Etched: Austin.
Ethernet appears in 0.7% of 2674 comparable senior other roles in United States; PCIe appears in 0.2% of 2674 comparable senior other roles in United States.

Quick facts

Is the Design Verification Engineer - Interface IP role remote?: No — this is an on-site role in San Jose.
How much experience is required?: At least 5 years of relevant experience for this Design Verification Engineer - Interface IP role.
Where is the role based?: Etched is hiring for this position in San Jose.
What's the tech stack?: Joblaze extracted these technologies from the posting: ARC, ARM, Ethernet, PCIe, SystemVerilog, UVM.
What seniority level is this role?: Etched targets senior candidates for this position.
Is this full-time or contract?: Full-time for this Design Verification Engineer - Interface IP role at Etched.

From the original posting

Job Summary

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities

End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
Understand vendor IP configurations and handle handshake with internal IP team
Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

5+ years of design verification experience
You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.
You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.
You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.
You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.

Strong candidates may also have experience with

Experience handling vendors and integration of IP/VIP’s
UVM/System Verilog

Benefits

Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
Housing subsidy of $2.5k per month for those living within walking distance of the office
Daily lunch + dinner in our office
Unlimited compute budget subject to ROI justification

Standard company text repeated across Etched's postings is omitted here.

Design Verification Engineer - Interface IP

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