"uvm" Jobs

12 open tech roles matching “uvm”, taken straight from company career pages — not reposted from other job boards. Most in demand right now: Python, UVM, ASIC. Every listing is re-checked daily and closed roles are removed.

Showing 12 of 12 results

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $125k–$195k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network, enhancing global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $135k–$210k/yr Published 1 month ago

Python UVM SystemVerilog MATLAB

Flexible on stack

Apply →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$260k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$260k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 1 month ago

ASIC VMM Python UVM OVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$300k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $210k–$300k/yr Published 3 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

Apply →