"digital asic design" Jobs

100 open tech roles matching “digital asic design”, taken straight from company career pages — not reposted from other job boards. Every listing is re-checked daily and closed roles are removed.

No "digital asic design" jobs in Berlin right now — showing "digital asic design" jobs in all locations.

Showing 20 of 100 results

Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $210k–$300k/yr Published 4 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $210k–$310k/yr Published 4 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Principal Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$300k/yr Published 4 months ago

FPGA ASIC VMM Python UVM

Flexible on stack

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Principal Verification Engineer

Join Jariet Technologies as a Principal Verification Engineer to develop cutting-edge verification methodologies for high-speed digital communication SoCs.

CesiumAstro Aliso Viejo, CA Published 2 weeks ago

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Principal ASIC Design Engineer (Starshield) Visa

SpaceX Hawthorne, CA $200k–$285k/yr Published 6 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. ASIC Design Engineer (Starshield)

SpaceX Hawthorne, CA $160k–$225k/yr Published 6 months ago

Xilinx Vivado Verilog IES Altera Quartus II Spyglass

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Sr. Staff SoC RTL Engineer

Join Ambiq as a Senior Staff SoC RTL Engineer to design and deliver ultra-low-power semiconductor solutions.

Ambiq Austin, Texas, United States Published 2 months ago

APB Verilog ARM AHB FPGA

Flexible on stack 70% coding

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Senior FPGA Prototyping Engineer

Join K2 Space as a Senior FPGA Prototyping Engineer to drive the development of next-gen communications ASICs in a fast-paced environment.

K2 Space United States - Remote $120k–$225k/yr Published 2 months ago

Verilog AMD UART JTAG Xilinx

Flexible on stack

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RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as an RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 2 months ago

Filters vector modulators low noise amplifiers Mixed-Signal Spread Spectrum

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RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as an RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $125k–$195k/yr Published 2 months ago

Filters vector modulators low noise amplifiers power amplifiers DSP

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AMS Verification Engineer (RFIC Engineering) Visa

Join SpaceX as an AMS Verification Engineer to develop cutting-edge RFICs for the Starlink network.

SpaceX Irvine, CA $125k–$160k/yr Published 1 month ago

AMS Verilog-A RFIC Python UVM

Flexible on stack

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RTL Intern

Join Etched as an RTL Intern to design microarchitecture and implement logic in Verilog while working on cutting-edge machine learning architectures.

Etched San Jose Published 3 weeks ago

Verilog ASIC Python UVM SystemVerilog

Flexible on stack

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AMS Verification Engineer (RFIC Engineering) Visa

Join SpaceX as an AMS Verification Engineer to develop cutting-edge RFICs for the Starlink network.

SpaceX Redmond, WA $125k–$200k/yr Published 1 month ago

AMS Verilog-A RFIC Python UVM

Flexible on stack

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Senior FPGA Prototyping Engineer

Join K2 Space as a Senior FPGA Prototyping Engineer to drive the development of next-gen communications ASICs in a fast-paced environment.

K2 Space Seattle, WA $120k–$225k/yr Published 2 months ago

Oscilloscopes Verilog AMD JTAG Xilinx

Flexible on stack

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Senior Post Silicon Validation Engineer (Bringup)

Join Graphcore as a Senior Post Silicon Validation Engineer to validate cutting-edge AI chips and lead a collaborative engineering team.

Graphcore Austin, Texas, United States $156.5k–$211.7k/yr Published 10 months ago

PCIe C++ ARM LPDDR FPGA

Flexible on stack

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Sr. DSP Systems Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. DSP Systems Engineer to develop cutting-edge ASICs for satellite broadband systems.

SpaceX Irvine, CA $165k–$265k/yr Published 2 months ago

RF/wireless system design AI/ML FPGA C/C++ ASIC

Flexible on stack AI-first team

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Sr. DSP Systems Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. DSP Systems Engineer to develop cutting-edge ASICs for satellite broadband systems.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 months ago

C++ RF MIMO FPGA ASIC

Flexible on stack

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Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 months ago

Filters vector modulators low noise amplifiers Mixed-Signal Spread Spectrum

Flexible on stack

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Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $165k–$265k/yr Published 2 months ago

DSP QAM Ka-band QPSK APSK

Flexible on stack

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Director - Post-Silicon Validation (Functional)

Lead a team in post-silicon validation of cutting-edge AI chips and platforms at Graphcore's new AI Engineering Campus in Austin.

Graphcore Austin, Texas, United States Published 4 days ago

C++ FPGA ASIC Python Linux

Flexible on stack

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