Join Etched as an RTL Intern to design microarchitecture and implement logic in Verilog while working on cutting-edge machine learning architectures.
Posted by employer 4 days ago
First seen on Joblaze 2 days ago
Last verified on the company career page 9 hours ago
What you'll build
- Design microarchitecture
- Implement logic in Verilog
- Contribute to RTL block development
- Participate in the full design cycle
- Learn about modern artificial intelligence
Must have
- Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field
- Familiarity with high-speed digital logic
Nice to have
- Exposure to ASIC or SoC design concepts
- Familiarity with verification work and writing test benches
- Familiarity with physical design flows and tooling
- Familiarity with modern ML and LLM model architectures
- Ability to program with Python or another scripting language
Practical constraints
- Interns needed for Fall '26, Spring '27, and Summer '27
Requirements
- Education
- Bachelor's degree
Not disclosed in this posting: compensation, years of experience, visa sponsorship.
Benefits
Joblaze summary
In the role of RTL Intern at Etched, the individual will engage in designing microarchitecture and implementing logic using Verilog, contributing to the development of RTL blocks and participating in the entire design cycle. Key skills include familiarity with high-speed digital logic, ASIC or SoC design concepts, and programming in SystemVerilog or Python. This position is suitable for students pursuing degrees in electrical or computer engineering, particularly those eager to learn in a fast-paced environment. Etched emphasizes a collaborative culture where engineering and research intersect, providing interns with direct mentorship from experienced professionals.
Joblaze insights
Quick facts
- Is the RTL Intern role remote?
- No — this is an on-site role in San Jose.
- Where is the role based?
- Etched is hiring for this position in San Jose.
- What's the tech stack?
- Joblaze extracted these technologies from the posting: ASIC, Python, SoC, SystemVerilog, UVM, Verilog.
- What seniority level is this role?
- Etched targets intern candidates for this position.
- Is this full-time or contract?
- Internship for this RTL Intern role at Etched.
From the original posting
Job Summary
As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Fall '26, Spring '27, and Summer '27 interns.
Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field.
Familiarity with high-speed digital logic
Exposure to ASIC or SoC design concepts
Familiarity with SystemVerilog, UVM, or Python
Familiarity with verification work and writing test benches
Familiarity with physical design flows and tooling
Are able to learn quickly about transformers and other aspects of modern artificial intelligence
Strong candidates may also have experience with
Familiarity with modern ML and LLM model architectures
Familiarity with numerical representations and functions
Familiarity with clocking and reset schemes
Ability to program with Python or another scripting language
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
12-week paid internship
Generous housing support for those relocating
Daily lunch and dinner in our office
Based at our office in San Jose, CA
Direct mentorship from industry leaders and world-class engineers
Opportunity to work on one of the most important problems of our time
For any questions, contact internships@etched.com
Standard company text repeated across Etched's postings is omitted here.