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ASIC Jobs

80 open positions · Updated 2 months ago

Average salary (USD/year): 186.0k–279.8k/yr

80 roles Senior 38, Mid 15, Principal 14, Lead 7, Director 2, Intern 2, Junior 1, Staff 1 1–18 yrs experience Aliso Viejo, CA +20 more Full-time, Internship newest 3 days ago

Also hiring: Python FPGA SoC CMOS DFT Perl

80 ASIC roles across 12 companies, most in Other; 3% fully remote; typical advertised salary $172.5k

Who is hiring (12 companies)

SpaceX (48) Etched (11) K2 Space (8) Anthropic (3) Graphcore (3)

Role types

Other (61) AI/ML (12) Management (3) Security (2) Design (1)

Work arrangement: 2 fully remote · 3 hybrid · 18 on-site · 57 not stated

Advertised salaries: p25 $165k · median $172.5k · p75 $197.5k (from 46 disclosed annual salaries, USD)

Counts are open roles Joblaze currently tracks on company career pages for this exact skill/location; salaries are advertised minimums, annual, converted to USD.

Showing 20 of 80 positions

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Principal RFIC Engineer (Starshield Silicon) Visa

Join SpaceX as a Principal RFIC Engineer to develop cutting-edge RFICs for national security applications in a fast-paced environment.

SpaceX Hawthorne, CA $210k–$340k/yr Published 2 months ago

GaAs GaN Network Analyzers Vector Signal Analyzers spectrum analyzers

Sr. DSP Systems Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. DSP Systems Engineer to develop cutting-edge ASICs for satellite broadband systems.

SpaceX Palo Alto, CA $175k–$280k/yr Published 2 months ago

C++ RF C MIMO FPGA

Flexible on stack

Sr. DSP Systems Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. DSP Systems Engineer to develop cutting-edge ASICs for satellite broadband systems.

SpaceX Irvine, CA $165k–$265k/yr Published 2 months ago

RF/wireless system design AI/ML FPGA C/C++ ASIC

Flexible on stack AI-first team

Principal Engineer, AI Satellites (Starmind) Visa

Join SpaceX as a Principal Engineer to develop cutting-edge RFICs for the Starmind satellite constellation.

SpaceX Bastrop, TX Published 2 months ago

RF Analog Mixed-Signal DSP microwave

ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Austin, TX Published 2 months ago

Verilog RTL DFT bash ASIC

Flexible on stack

ASIC/SOC DFT Engineer (Silicon Engineering) Visa

Join SpaceX as an ASIC/SOC DFT Engineer to develop cutting-edge ASICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $135k–$175k/yr Published 2 months ago

Verilog UPF RTL DFT ASIC

Flexible on stack

Technical Program Manager, Silicon Hybrid Visa

Own the end-to-end execution of custom silicon for AI systems at Anthropic, driving external partnerships and program management.

Anthropic San Francisco, CA | New York City, NY $365k–$435k/yr Published 2 months ago

hardware-software co-design DFT silicon ASIC analog/mixed-signal

Hardware Systems Architect Hybrid Visa

Join Anthropic as a Hardware Systems Architect to lead the design and architecture of cutting-edge AI hardware systems.

Anthropic San Francisco, CA | New York City, NY | Seattle, WA $320k–$485k/yr Published 2 months ago

HVDC 48V BMC platform firmware Power integrity

Flexible on stack

Electrical Design Engineer, Satellites Payload (Starlink) Visa

Join SpaceX as an Electrical Design Engineer to develop high-reliability electronics for the Starlink satellite communication network.

SpaceX Palo Alto, CA $115k–$185k/yr Published 2 months ago

C++ RF PAM4 C PCB

Flexible on stack

Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to lead the development of next-generation ASICs for the Starlink network.

SpaceX Irvine, CA $210k–$340k/yr Published 3 months ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

Principal DFT Engineer (Silicon Engineering) Visa

Lead the implementation and optimization of DFT architectures for next-generation ASICs at SpaceX.

SpaceX Austin, TX Published 3 months ago

C++ Verilog Siemens Tessent UPF DFT

Flexible on stack

Principal DFT Engineer (Silicon Engineering) Visa

Join SpaceX as a Principal DFT Engineer to develop next-generation ASICs for the Starlink network, enhancing global connectivity.

SpaceX Palo Alto, CA $220k–$355k/yr Published 3 months ago

C++ Verilog Siemens Tessent DFT ASIC

Flexible on stack

Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $165k–$265k/yr Published 3 months ago

DSP QAM Ka-band QPSK APSK

Flexible on stack

Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Palo Alto, CA $175k–$280k/yr Published 3 months ago

Filters vector modulators low noise amplifiers Mixed-Signal Spread Spectrum

Flexible on stack

Sr. RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as a Sr. RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Redmond, WA $165k–$270k/yr Published 3 months ago

DSP Ka-band microwave SiGe RFIC

Flexible on stack

RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as an RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Irvine, CA $125k–$195k/yr Published 3 months ago

Filters vector modulators low noise amplifiers power amplifiers DSP

RFIC Design Engineer (RFIC Engineering) Visa

Join SpaceX as an RFIC Design Engineer to develop cutting-edge RFICs for the Starlink network, enabling global connectivity.

SpaceX Redmond, WA $125k–$195k/yr Published 3 months ago

Filters vector modulators low noise amplifiers Mixed-Signal Spread Spectrum

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Redmond, WA $165k–$260k/yr Published 3 months ago

ASIC VMM Python UVM OVM

Flexible on stack

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Palo Alto, CA $175k–$280k/yr Published 3 months ago

ASIC VMM Python UVM OVM

Flexible on stack

Sr. ASIC Design Verification Engineer (Silicon Engineering) Visa

Join SpaceX as a Sr. ASIC Design Verification Engineer to develop cutting-edge ASICs for the Starlink network.

SpaceX Irvine, CA $165k–$260k/yr Published 3 months ago

ASIC VMM Python UVM OVM

Flexible on stack

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